From ee70d8cfc430e38b84945e8b9ea870585b98f87c Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 12:01:31 -0400 Subject: [PATCH 01/10] bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. src/base/bitfield.hh: bit_val was being used directly in the statement in return. If type B had fewer bits than last, bit_val << last would get the wrong answer. --HG-- extra : convert_revision : cbc43ccd139f82ebbd65f30af5d05b87c4edac64 --- src/base/bitfield.hh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/base/bitfield.hh b/src/base/bitfield.hh index 69cce2245..518bad6b8 100644 --- a/src/base/bitfield.hh +++ b/src/base/bitfield.hh @@ -96,8 +96,9 @@ inline T insertBits(T val, int first, int last, B bit_val) { + T t_bit_val = bit_val; T bmask = mask(first - last + 1) << last; - return ((bit_val << last) & bmask) | (val & ~bmask); + return ((t_bit_val << last) & bmask) | (val & ~bmask); } /** From ff55888575af9e661697882736741ea6d4613303 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:23:01 -0400 Subject: [PATCH 02/10] undo my previous bus change, it can make the bus deadlock.. so it still constantly reschedules itself --HG-- extra : convert_revision : b5ef1aa0a6a2e32bd775d2dbcad9cd9505ad9b78 --- src/mem/bus.cc | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/src/mem/bus.cc b/src/mem/bus.cc index 6682ade55..95d4e2873 100644 --- a/src/mem/bus.cc +++ b/src/mem/bus.cc @@ -171,8 +171,9 @@ bool Bus::recvTiming(PacketPtr pkt) { Port *port; - DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s\n", - pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString()); + DPRINTF(Bus, "recvTiming: packet src %d dest %d addr 0x%x cmd %s result %d\n", + pkt->getSrc(), pkt->getDest(), pkt->getAddr(), pkt->cmdString(), + pkt->result); BusPort *pktPort; if (pkt->getSrc() == defaultId) @@ -272,20 +273,14 @@ Bus::recvRetry(int id) retryList.pop_front(); inRetry = false; - if (id != -1) { - //Bring tickNextIdle up to the present - while (tickNextIdle < curTick) - tickNextIdle += clock; - - //Burn a cycle for the missed grant. + //Bring tickNextIdle up to the present + while (tickNextIdle < curTick) tickNextIdle += clock; - if (!busIdle.scheduled()) { - busIdle.schedule(tickNextIdle); - } else { - busIdle.reschedule(tickNextIdle); - } - } // id != -1 + //Burn a cycle for the missed grant. + tickNextIdle += clock; + + busIdle.reschedule(tickNextIdle, true); } } //If we weren't able to drain before, we might be able to now. From 9dfbea68a204ca93ef9d20a13dd2fe7288121c75 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:34:54 -0400 Subject: [PATCH 03/10] update for new reschedule semantics --HG-- extra : convert_revision : 8c18b2513d638f67cc096e7f1483b47390a374ca --- src/dev/i8254xGBe.cc | 16 ++++------------ src/dev/io_device.cc | 5 +---- src/dev/ns_gige.cc | 5 +---- src/dev/sinic.cc | 5 +---- src/sim/eventq.hh | 17 ++++++++++++----- src/sim/pseudo_inst.cc | 10 ++-------- 6 files changed, 21 insertions(+), 37 deletions(-) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index e54249dee..680e31656 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -727,12 +727,8 @@ IGbE::RxDescCache::pktComplete() if (igbe->regs.rdtr.delay()) { DPRINTF(EthernetSM, "RXS: Scheduling DTR for %d\n", igbe->regs.rdtr.delay() * igbe->intClock()); - if (igbe->rdtrEvent.scheduled()) - igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() * - igbe->intClock()); - else - igbe->rdtrEvent.schedule(curTick + igbe->regs.rdtr.delay() * - igbe->intClock()); + igbe->rdtrEvent.reschedule(curTick + igbe->regs.rdtr.delay() * + igbe->intClock(),true); } if (igbe->regs.radv.idv() && igbe->regs.rdtr.delay()) { @@ -946,12 +942,8 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "Descriptor had IDE set\n"); if (igbe->regs.tidv.idv()) { DPRINTF(EthernetDesc, "setting tidv\n"); - if (igbe->tidvEvent.scheduled()) - igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() * - igbe->intClock()); - else - igbe->tidvEvent.schedule(curTick + igbe->regs.tidv.idv() * - igbe->intClock()); + igbe->tidvEvent.reschedule(curTick + igbe->regs.tidv.idv() * + igbe->intClock(), true); } if (igbe->regs.tadv.idv() && igbe->regs.tidv.idv()) { diff --git a/src/dev/io_device.cc b/src/dev/io_device.cc index 9384c4b92..d430ace72 100644 --- a/src/dev/io_device.cc +++ b/src/dev/io_device.cc @@ -111,10 +111,7 @@ DmaPort::recvTiming(PacketPtr pkt) else if (backoffTime < device->maxBackoffDelay) backoffTime <<= 1; - if (backoffEvent.scheduled()) - backoffEvent.reschedule(curTick + backoffTime); - else - backoffEvent.schedule(curTick + backoffTime); + backoffEvent.reschedule(curTick + backoffTime, true); DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime); diff --git a/src/dev/ns_gige.cc b/src/dev/ns_gige.cc index bec1fb848..d9985f808 100644 --- a/src/dev/ns_gige.cc +++ b/src/dev/ns_gige.cc @@ -2310,10 +2310,7 @@ NSGigE::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - if (txEvent.scheduled()) - txEvent.reschedule(curTick + cycles(1)); - else - txEvent.schedule(curTick + cycles(1)); + txEvent.reschedule(curTick + cycles(1), true); } bool diff --git a/src/dev/sinic.cc b/src/dev/sinic.cc index 1a72652da..420761620 100644 --- a/src/dev/sinic.cc +++ b/src/dev/sinic.cc @@ -1199,10 +1199,7 @@ Device::transferDone() DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n"); - if (txEvent.scheduled()) - txEvent.reschedule(curTick + cycles(1)); - else - txEvent.schedule(curTick + cycles(1)); + txEvent.reschedule(curTick + cycles(1), true); } bool diff --git a/src/sim/eventq.hh b/src/sim/eventq.hh index a57e9077e..974313968 100644 --- a/src/sim/eventq.hh +++ b/src/sim/eventq.hh @@ -210,7 +210,8 @@ class Event : public Serializable, public FastAlloc void schedule(Tick t); /// Reschedule the event with the current priority - void reschedule(Tick t); + // always parameter means to schedule if not already scheduled + void reschedule(Tick t, bool always = false); /// Remove the event from the current schedule void deschedule(); @@ -402,16 +403,22 @@ Event::deschedule() } inline void -Event::reschedule(Tick t) +Event::reschedule(Tick t, bool always) { - assert(scheduled()); - clearFlags(Squashed); + assert(scheduled() || always); #if TRACING_ON when_scheduled = curTick; #endif _when = t; - queue->reschedule(this); + + if (scheduled()) { + clearFlags(Squashed); + queue->reschedule(this); + } else { + setFlags(Scheduled); + queue->schedule(this); + } } inline void diff --git a/src/sim/pseudo_inst.cc b/src/sim/pseudo_inst.cc index 56a779674..10127aa5f 100644 --- a/src/sim/pseudo_inst.cc +++ b/src/sim/pseudo_inst.cc @@ -87,10 +87,7 @@ namespace PseudoInst Tick resume = curTick + Clock::Int::ns * ns; - if (quiesceEvent->scheduled()) - quiesceEvent->reschedule(resume); - else - quiesceEvent->schedule(resume); + quiesceEvent->reschedule(resume, true); DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n", tc->getCpuPtr()->name(), ns, resume); @@ -110,10 +107,7 @@ namespace PseudoInst Tick resume = curTick + tc->getCpuPtr()->cycles(cycles); - if (quiesceEvent->scheduled()) - quiesceEvent->reschedule(resume); - else - quiesceEvent->schedule(resume); + quiesceEvent->reschedule(resume, true); DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n", tc->getCpuPtr()->name(), cycles, resume); From 69ea50c1635bc3dc455eeb29a6f7b0ff04e4ad0b Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Wed, 9 May 2007 22:39:43 -0400 Subject: [PATCH 04/10] couple of updates in the intel nic --HG-- extra : convert_revision : da68e5e6411000d9d5247f769ee528a443286c61 --- src/dev/i8254xGBe.cc | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/dev/i8254xGBe.cc b/src/dev/i8254xGBe.cc index 680e31656..e0272c655 100644 --- a/src/dev/i8254xGBe.cc +++ b/src/dev/i8254xGBe.cc @@ -891,6 +891,7 @@ IGbE::TxDescCache::pktComplete() pktPtr = NULL; DPRINTF(EthernetDesc, "Partial Packet Descriptor Done\n"); + enableSm(); return; } @@ -971,6 +972,7 @@ IGbE::TxDescCache::pktComplete() DPRINTF(EthernetDesc, "used > WTHRESH, writing back descriptor\n"); writeback((igbe->cacheBlockSize()-1)>>4); } + enableSm(); igbe->checkDrain(); } @@ -1150,6 +1152,8 @@ IGbE::txStateMachine() return; } + DPRINTF(EthernetSM, "TXS: Nothing to do, stopping ticking\n"); + txTick = false; } bool From 4a37c48e8e74405c39899e4914656930869f8bd4 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:08:22 -0400 Subject: [PATCH 05/10] add/update parameters for bus bridge --HG-- extra : convert_revision : 063f757fbfa2c613328ffa70e556f8926623fa91 --- src/python/m5/objects/Bridge.py | 7 +++++-- src/python/m5/objects/Device.py | 6 ++++++ 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/python/m5/objects/Bridge.py b/src/python/m5/objects/Bridge.py index e123c2891..33b24ad3c 100644 --- a/src/python/m5/objects/Bridge.py +++ b/src/python/m5/objects/Bridge.py @@ -5,9 +5,12 @@ class Bridge(MemObject): type = 'Bridge' side_a = Port('Side A port') side_b = Port('Side B port') - queue_size_a = Param.Int(16, "The number of requests to buffer") - queue_size_b = Param.Int(16, "The number of requests to buffer") + req_size_a = Param.Int(16, "The number of requests to buffer") + req_size_b = Param.Int(16, "The number of requests to buffer") + resp_size_a = Param.Int(16, "The number of requests to buffer") + resp_size_b = Param.Int(16, "The number of requests to buffer") delay = Param.Latency('0ns', "The latency of this bridge") + nack_delay = Param.Latency('0ns', "The latency of this bridge") write_ack = Param.Bool(False, "Should this bridge ack writes") fix_partial_write_a = Param.Bool(False, "Should this bridge fixup partial block writes") fix_partial_write_b = Param.Bool(False, "Should this bridge fixup partial block writes") diff --git a/src/python/m5/objects/Device.py b/src/python/m5/objects/Device.py index f4b873a60..90fbfb552 100644 --- a/src/python/m5/objects/Device.py +++ b/src/python/m5/objects/Device.py @@ -19,6 +19,12 @@ class DmaDevice(PioDevice): type = 'DmaDevice' abstract = True dma = Port(Self.pio.peerObj.port, "DMA port") + min_backoff_delay = Param.Latency('4ns', + "min time between a nack packet being received and the next request made by the device") + max_backoff_delay = Param.Latency('10us', + "max time between a nack packet being received and the next request made by the device") + + class IsaFake(BasicPioDevice): type = 'IsaFake' From 77fd734b997f6d63edf4a84447fc76b38088bfa3 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 00:30:53 -0400 Subject: [PATCH 06/10] update for bus bridge updates --HG-- extra : convert_revision : 829b1f33c88f1708ce5ee84afb4cd8bda8a6576f --- .../tsunami-simple-timing-dual/config.ini | 27 +++- .../tsunami-simple-timing-dual/config.out | 27 +++- .../tsunami-simple-timing-dual/m5stats.txt | 139 +++++++++--------- .../linux/tsunami-simple-timing/config.ini | 27 +++- .../linux/tsunami-simple-timing/config.out | 27 +++- .../linux/tsunami-simple-timing/m5stats.txt | 103 +++++++------ 6 files changed, 196 insertions(+), 154 deletions(-) diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini index b24dc5968..8e1ba179d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu0 cpu1 disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/Users/ali/work/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/Users/ali/work/system/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/Users/ali/work/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -22,8 +22,13 @@ system_type=34 [system.bridge] type=Bridge delay=0 -queue_size_a=16 -queue_size_b=16 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] @@ -108,7 +113,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk2] @@ -127,7 +132,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -136,6 +141,7 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=true @@ -146,6 +152,7 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false @@ -193,7 +200,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.tsunami] @@ -242,6 +249,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=20000 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=1 pci_func=0 @@ -614,6 +623,8 @@ children=configdata config_latency=40 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out index b41d5083f..890030c19 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out @@ -14,9 +14,9 @@ type=LinuxAlphaSystem boot_cpu_frequency=1 physmem=system.physmem mem_mode=timing -kernel=/dist/m5/system/binaries/vmlinux -console=/dist/m5/system/binaries/console -pal=/dist/m5/system/binaries/ts_osfpal +kernel=/Users/ali/work/system/binaries/vmlinux +console=/Users/ali/work/system/binaries/console +pal=/Users/ali/work/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -30,6 +30,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -57,14 +58,19 @@ system=system [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 delay=0 +nack_delay=0 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -82,7 +88,7 @@ delay=2000 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -162,7 +168,7 @@ function_trace_start=0 [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -510,6 +516,8 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -632,6 +640,8 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -646,4 +656,5 @@ bus_id=0 clock=2 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt index 24b2c4738..e808b031d 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt @@ -1,31 +1,30 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 249273 # Simulator instruction rate (inst/s) -host_mem_usage 249952 # Number of bytes of host memory used -host_seconds 261.36 # Real time elapsed on the host -host_tick_rate 15217956 # Simulator tick rate (ticks/s) +host_inst_rate 159511 # Simulator instruction rate (inst/s) +host_seconds 408.44 # Real time elapsed on the host +host_tick_rate 9737848 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 65149861 # Number of instructions simulated -sim_seconds 1.988682 # Number of seconds simulated -sim_ticks 3977364868 # Number of ticks simulated +sim_insts 65151264 # Number of instructions simulated +sim_seconds 1.988681 # Number of seconds simulated +sim_ticks 3977362808 # Number of ticks simulated system.cpu0.dtb.accesses 676531 # DTB accesses system.cpu0.dtb.acv 306 # DTB access violations -system.cpu0.dtb.hits 12726821 # DTB hits +system.cpu0.dtb.hits 12726999 # DTB hits system.cpu0.dtb.misses 8261 # DTB misses system.cpu0.dtb.read_accesses 494241 # DTB read accesses system.cpu0.dtb.read_acv 184 # DTB read access violations -system.cpu0.dtb.read_hits 7906586 # DTB read hits +system.cpu0.dtb.read_hits 7906690 # DTB read hits system.cpu0.dtb.read_misses 7534 # DTB read misses system.cpu0.dtb.write_accesses 182290 # DTB write accesses system.cpu0.dtb.write_acv 122 # DTB write access violations -system.cpu0.dtb.write_hits 4820235 # DTB write hits +system.cpu0.dtb.write_hits 4820309 # DTB write hits system.cpu0.dtb.write_misses 727 # DTB write misses -system.cpu0.idle_fraction 0.930925 # Percentage of idle cycles -system.cpu0.itb.accesses 3412128 # ITB accesses +system.cpu0.idle_fraction 0.930953 # Percentage of idle cycles +system.cpu0.itb.accesses 3412195 # ITB accesses system.cpu0.itb.acv 161 # ITB acv -system.cpu0.itb.hits 3408295 # ITB hits +system.cpu0.itb.hits 3408362 # ITB hits system.cpu0.itb.misses 3833 # ITB misses -system.cpu0.kern.callpal 142543 # number of callpals executed +system.cpu0.kern.callpal 142550 # number of callpals executed system.cpu0.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu0.kern.callpal_wripir 572 0.40% 0.40% # number of callpals executed system.cpu0.kern.callpal_wrmces 1 0.00% 0.40% # number of callpals executed @@ -34,7 +33,7 @@ system.cpu0.kern.callpal_wrvptptr 1 0.00% 0.40% # nu system.cpu0.kern.callpal_swpctx 2878 2.02% 2.42% # number of callpals executed system.cpu0.kern.callpal_tbi 47 0.03% 2.46% # number of callpals executed system.cpu0.kern.callpal_wrent 7 0.00% 2.46% # number of callpals executed -system.cpu0.kern.callpal_swpipl 127693 89.58% 92.04% # number of callpals executed +system.cpu0.kern.callpal_swpipl 127700 89.58% 92.04% # number of callpals executed system.cpu0.kern.callpal_rdps 6611 4.64% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrkgp 1 0.00% 96.68% # number of callpals executed system.cpu0.kern.callpal_wrusp 3 0.00% 96.68% # number of callpals executed @@ -44,44 +43,44 @@ system.cpu0.kern.callpal_rti 4215 2.96% 99.65% # nu system.cpu0.kern.callpal_callsys 355 0.25% 99.90% # number of callpals executed system.cpu0.kern.callpal_imb 147 0.10% 100.00% # number of callpals executed system.cpu0.kern.inst.arm 0 # number of arm instructions executed -system.cpu0.kern.inst.hwrei 157728 # number of hwrei instructions executed -system.cpu0.kern.inst.quiesce 6621 # number of quiesce instructions executed -system.cpu0.kern.ipl_count 134531 # number of times we switched to this ipl -system.cpu0.kern.ipl_count_0 53714 39.93% 39.93% # number of times we switched to this ipl +system.cpu0.kern.inst.hwrei 157735 # number of hwrei instructions executed +system.cpu0.kern.inst.quiesce 6620 # number of quiesce instructions executed +system.cpu0.kern.ipl_count 134538 # number of times we switched to this ipl +system.cpu0.kern.ipl_count_0 53716 39.93% 39.93% # number of times we switched to this ipl system.cpu0.kern.ipl_count_21 131 0.10% 40.02% # number of times we switched to this ipl system.cpu0.kern.ipl_count_22 2009 1.49% 41.52% # number of times we switched to this ipl system.cpu0.kern.ipl_count_30 482 0.36% 41.88% # number of times we switched to this ipl -system.cpu0.kern.ipl_count_31 78195 58.12% 100.00% # number of times we switched to this ipl -system.cpu0.kern.ipl_good 108736 # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_0 53298 49.02% 49.02% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_count_31 78200 58.12% 100.00% # number of times we switched to this ipl +system.cpu0.kern.ipl_good 108740 # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_0 53300 49.02% 49.02% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_21 131 0.12% 49.14% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_22 2009 1.85% 50.98% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_good_30 482 0.44% 51.43% # number of times we switched to this ipl from a different ipl -system.cpu0.kern.ipl_good_31 52816 48.57% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu0.kern.ipl_good_31 52818 48.57% 100.00% # number of times we switched to this ipl from a different ipl system.cpu0.kern.ipl_ticks 3976579702 # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_0 3843537444 96.65% 96.65% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_0 3843619308 96.66% 96.66% # number of cycles we spent at this ipl system.cpu0.kern.ipl_ticks_21 123584 0.00% 96.66% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_22 1875640 0.05% 96.70% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.73% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_ticks_31 129841282 3.27% 100.00% # number of cycles we spent at this ipl -system.cpu0.kern.ipl_used 0.808260 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_0 0.992255 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_ticks_22 1873872 0.05% 96.71% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_30 1201752 0.03% 96.74% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_ticks_31 129761186 3.26% 100.00% # number of cycles we spent at this ipl +system.cpu0.kern.ipl_used 0.808247 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.ipl_used_0 0.992256 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu0.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.ipl_used_31 0.675440 # fraction of swpipl calls that actually changed the ipl -system.cpu0.kern.mode_good_kernel 1191 -system.cpu0.kern.mode_good_user 1191 +system.cpu0.kern.ipl_used_31 0.675422 # fraction of swpipl calls that actually changed the ipl +system.cpu0.kern.mode_good_kernel 1193 +system.cpu0.kern.mode_good_user 1193 system.cpu0.kern.mode_good_idle 0 system.cpu0.kern.mode_switch_kernel 6700 # number of protection mode switches -system.cpu0.kern.mode_switch_user 1191 # number of protection mode switches +system.cpu0.kern.mode_switch_user 1193 # number of protection mode switches system.cpu0.kern.mode_switch_idle 0 # number of protection mode switches -system.cpu0.kern.mode_switch_good 0.301863 # fraction of useful protection mode switches -system.cpu0.kern.mode_switch_good_kernel 0.177761 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good 0.302293 # fraction of useful protection mode switches +system.cpu0.kern.mode_switch_good_kernel 0.178060 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu0.kern.mode_switch_good_idle # fraction of useful protection mode switches -system.cpu0.kern.mode_ticks_kernel 3965299112 99.76% 99.76% # number of ticks spent at the given mode -system.cpu0.kern.mode_ticks_user 9599258 0.24% 100.00% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_kernel 3965295376 99.76% 99.76% # number of ticks spent at the given mode +system.cpu0.kern.mode_ticks_user 9600934 0.24% 100.00% # number of ticks spent at the given mode system.cpu0.kern.mode_ticks_idle 0 0.00% 100.00% # number of ticks spent at the given mode system.cpu0.kern.swap_context 2879 # number of times the context was actually changed system.cpu0.kern.syscall 216 # number of syscalls executed @@ -115,36 +114,36 @@ system.cpu0.kern.syscall_98 2 0.93% 97.69% # nu system.cpu0.kern.syscall_132 2 0.93% 98.61% # number of syscalls executed system.cpu0.kern.syscall_144 1 0.46% 99.07% # number of syscalls executed system.cpu0.kern.syscall_147 2 0.93% 100.00% # number of syscalls executed -system.cpu0.not_idle_fraction 0.069075 # Percentage of non-idle cycles +system.cpu0.not_idle_fraction 0.069047 # Percentage of non-idle cycles system.cpu0.numCycles 3976579942 # number of cpu cycles simulated -system.cpu0.num_insts 50251391 # Number of instructions executed -system.cpu0.num_refs 12958546 # Number of memory references +system.cpu0.num_insts 50252314 # Number of instructions executed +system.cpu0.num_refs 12958725 # Number of memory references system.cpu1.dtb.accesses 346252 # DTB accesses system.cpu1.dtb.acv 67 # DTB access violations -system.cpu1.dtb.hits 4740978 # DTB hits +system.cpu1.dtb.hits 4740996 # DTB hits system.cpu1.dtb.misses 3345 # DTB misses system.cpu1.dtb.read_accesses 235843 # DTB read accesses system.cpu1.dtb.read_acv 26 # DTB read access violations -system.cpu1.dtb.read_hits 2707473 # DTB read hits +system.cpu1.dtb.read_hits 2707487 # DTB read hits system.cpu1.dtb.read_misses 2918 # DTB read misses system.cpu1.dtb.write_accesses 110409 # DTB write accesses system.cpu1.dtb.write_acv 41 # DTB write access violations -system.cpu1.dtb.write_hits 2033505 # DTB write hits +system.cpu1.dtb.write_hits 2033509 # DTB write hits system.cpu1.dtb.write_misses 427 # DTB write misses -system.cpu1.idle_fraction 0.974575 # Percentage of idle cycles -system.cpu1.itb.accesses 2097220 # ITB accesses +system.cpu1.idle_fraction 0.974578 # Percentage of idle cycles +system.cpu1.itb.accesses 2097175 # ITB accesses system.cpu1.itb.acv 23 # ITB acv -system.cpu1.itb.hits 2095948 # ITB hits +system.cpu1.itb.hits 2095903 # ITB hits system.cpu1.itb.misses 1272 # ITB misses -system.cpu1.kern.callpal 80965 # number of callpals executed +system.cpu1.kern.callpal 80960 # number of callpals executed system.cpu1.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu1.kern.callpal_wripir 482 0.60% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrmces 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal_wrfen 1 0.00% 0.60% # number of callpals executed system.cpu1.kern.callpal_swpctx 2289 2.83% 3.43% # number of callpals executed -system.cpu1.kern.callpal_tbi 7 0.01% 3.43% # number of callpals executed +system.cpu1.kern.callpal_tbi 7 0.01% 3.44% # number of callpals executed system.cpu1.kern.callpal_wrent 7 0.01% 3.44% # number of callpals executed -system.cpu1.kern.callpal_swpipl 71577 88.40% 91.85% # number of callpals executed +system.cpu1.kern.callpal_swpipl 71572 88.40% 91.85% # number of callpals executed system.cpu1.kern.callpal_rdps 2303 2.84% 94.69% # number of callpals executed system.cpu1.kern.callpal_wrkgp 1 0.00% 94.69% # number of callpals executed system.cpu1.kern.callpal_wrusp 4 0.00% 94.70% # number of callpals executed @@ -155,28 +154,28 @@ system.cpu1.kern.callpal_callsys 162 0.20% 99.96% # nu system.cpu1.kern.callpal_imb 33 0.04% 100.00% # number of callpals executed system.cpu1.kern.callpal_rdunique 1 0.00% 100.00% # number of callpals executed system.cpu1.kern.inst.arm 0 # number of arm instructions executed -system.cpu1.kern.inst.hwrei 88247 # number of hwrei instructions executed +system.cpu1.kern.inst.hwrei 88242 # number of hwrei instructions executed system.cpu1.kern.inst.quiesce 2815 # number of quiesce instructions executed -system.cpu1.kern.ipl_count 78243 # number of times we switched to this ipl -system.cpu1.kern.ipl_count_0 30463 38.93% 38.93% # number of times we switched to this ipl +system.cpu1.kern.ipl_count 78238 # number of times we switched to this ipl +system.cpu1.kern.ipl_count_0 30461 38.93% 38.93% # number of times we switched to this ipl system.cpu1.kern.ipl_count_22 2001 2.56% 41.49% # number of times we switched to this ipl system.cpu1.kern.ipl_count_30 572 0.73% 42.22% # number of times we switched to this ipl -system.cpu1.kern.ipl_count_31 45207 57.78% 100.00% # number of times we switched to this ipl -system.cpu1.kern.ipl_good 61005 # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_0 29502 48.36% 48.36% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_count_31 45204 57.78% 100.00% # number of times we switched to this ipl +system.cpu1.kern.ipl_good 61001 # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_good_0 29500 48.36% 48.36% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_22 2001 3.28% 51.64% # number of times we switched to this ipl from a different ipl system.cpu1.kern.ipl_good_30 572 0.94% 52.58% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_good_31 28930 47.42% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu1.kern.ipl_ticks 3977363084 # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_0 3855395406 96.93% 96.93% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_22 1873360 0.05% 96.98% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_good_31 28928 47.42% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu1.kern.ipl_ticks 3977361024 # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_0 3855399740 96.93% 96.93% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_ticks_22 1871566 0.05% 96.98% # number of cycles we spent at this ipl system.cpu1.kern.ipl_ticks_30 1461344 0.04% 97.02% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_ticks_31 118632974 2.98% 100.00% # number of cycles we spent at this ipl -system.cpu1.kern.ipl_used 0.779686 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_0 0.968454 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_ticks_31 118628374 2.98% 100.00% # number of cycles we spent at this ipl +system.cpu1.kern.ipl_used 0.779685 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_0 0.968451 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.ipl_used_30 1 # fraction of swpipl calls that actually changed the ipl -system.cpu1.kern.ipl_used_31 0.639945 # fraction of swpipl calls that actually changed the ipl +system.cpu1.kern.ipl_used_31 0.639943 # fraction of swpipl calls that actually changed the ipl system.cpu1.kern.mode_good_kernel 1058 system.cpu1.kern.mode_good_user 562 system.cpu1.kern.mode_good_idle 496 @@ -187,9 +186,9 @@ system.cpu1.kern.mode_switch_good 0.353020 # fr system.cpu1.kern.mode_switch_good_kernel 0.441385 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_user 1 # fraction of useful protection mode switches system.cpu1.kern.mode_switch_good_idle 0.163427 # fraction of useful protection mode switches -system.cpu1.kern.mode_ticks_kernel 64042452 1.61% 1.61% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_user 5753306 0.14% 1.75% # number of ticks spent at the given mode -system.cpu1.kern.mode_ticks_idle 3907567318 98.25% 100.00% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_kernel 64032120 1.61% 1.61% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_user 5754658 0.14% 1.75% # number of ticks spent at the given mode +system.cpu1.kern.mode_ticks_idle 3907574238 98.25% 100.00% # number of ticks spent at the given mode system.cpu1.kern.swap_context 2290 # number of times the context was actually changed system.cpu1.kern.syscall 110 # number of syscalls executed system.cpu1.kern.syscall_2 1 0.91% 0.91% # number of syscalls executed @@ -213,10 +212,10 @@ system.cpu1.kern.syscall_90 1 0.91% 95.45% # nu system.cpu1.kern.syscall_92 2 1.82% 97.27% # number of syscalls executed system.cpu1.kern.syscall_132 2 1.82% 99.09% # number of syscalls executed system.cpu1.kern.syscall_144 1 0.91% 100.00% # number of syscalls executed -system.cpu1.not_idle_fraction 0.025425 # Percentage of non-idle cycles -system.cpu1.numCycles 3977364868 # number of cpu cycles simulated -system.cpu1.num_insts 14898470 # Number of instructions executed -system.cpu1.num_refs 4770918 # Number of memory references +system.cpu1.not_idle_fraction 0.025422 # Percentage of non-idle cycles +system.cpu1.numCycles 3977362808 # number of cpu cycles simulated +system.cpu1.num_insts 14898950 # Number of instructions executed +system.cpu1.num_refs 4770935 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini index 9edee8632..65aa9c7e6 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini @@ -8,11 +8,11 @@ type=LinuxAlphaSystem children=bridge cpu disk0 disk2 intrctrl iobus membus physmem sim_console simple_disk tsunami boot_cpu_frequency=1 boot_osflags=root=/dev/hda1 console=ttyS0 -console=/dist/m5/system/binaries/console +console=/Users/ali/work/system/binaries/console init_param=0 -kernel=/dist/m5/system/binaries/vmlinux +kernel=/Users/ali/work/system/binaries/vmlinux mem_mode=timing -pal=/dist/m5/system/binaries/ts_osfpal +pal=/Users/ali/work/system/binaries/ts_osfpal physmem=system.physmem readfile=tests/halt.sh symbolfile= @@ -22,8 +22,13 @@ system_type=34 [system.bridge] type=Bridge delay=0 -queue_size_a=16 -queue_size_b=16 +fix_partial_write_a=false +fix_partial_write_b=true +nack_delay=0 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 write_ack=false side_a=system.iobus.port[0] side_b=system.membus.port[0] @@ -76,7 +81,7 @@ table_size=65536 [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk2] @@ -95,7 +100,7 @@ table_size=65536 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.intrctrl] @@ -104,6 +109,7 @@ sys=system [system.iobus] type=Bus +block_size=64 bus_id=0 clock=2 responder_set=true @@ -114,6 +120,7 @@ port=system.bridge.side_a system.tsunami.cchip.pio system.tsunami.pchip.pio syst [system.membus] type=Bus children=responder +block_size=64 bus_id=1 clock=2 responder_set=false @@ -161,7 +168,7 @@ system=system [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.tsunami] @@ -210,6 +217,8 @@ dma_write_delay=0 dma_write_factor=0 hardware_address=00:90:00:00:00:01 intr_delay=20000 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=1 pci_func=0 @@ -582,6 +591,8 @@ children=configdata config_latency=40 configdata=system.tsunami.ide.configdata disks=system.disk0 system.disk2 +max_backoff_delay=20000 +min_backoff_delay=8 pci_bus=0 pci_dev=0 pci_func=0 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out index ad8a29167..1034abd0e 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out @@ -14,9 +14,9 @@ type=LinuxAlphaSystem boot_cpu_frequency=1 physmem=system.physmem mem_mode=timing -kernel=/dist/m5/system/binaries/vmlinux -console=/dist/m5/system/binaries/console -pal=/dist/m5/system/binaries/ts_osfpal +kernel=/Users/ali/work/system/binaries/vmlinux +console=/Users/ali/work/system/binaries/console +pal=/Users/ali/work/system/binaries/ts_osfpal boot_osflags=root=/dev/hda1 console=ttyS0 readfile=tests/halt.sh symbolfile= @@ -30,6 +30,7 @@ bus_id=1 clock=2 width=64 responder_set=false +block_size=64 [system.intrctrl] type=IntrControl @@ -57,14 +58,19 @@ system=system [system.bridge] type=Bridge -queue_size_a=16 -queue_size_b=16 +req_size_a=16 +req_size_b=16 +resp_size_a=16 +resp_size_b=16 delay=0 +nack_delay=0 write_ack=false +fix_partial_write_a=false +fix_partial_write_b=true [system.disk0.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.disk0.image] @@ -82,7 +88,7 @@ delay=2000 [system.disk2.image.child] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-bigswap2.img +image_file=/Users/ali/work/system/disks/linux-bigswap2.img read_only=true [system.disk2.image] @@ -100,7 +106,7 @@ delay=2000 [system.simple_disk.disk] type=RawDiskImage -image_file=/dist/m5/system/disks/linux-latest.img +image_file=/Users/ali/work/system/disks/linux-latest.img read_only=true [system.simple_disk] @@ -479,6 +485,8 @@ BAR5Size=0 type=NSGigE system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ethernet.configdata pci_bus=0 pci_dev=1 @@ -601,6 +609,8 @@ BAR5Size=0 type=IdeController system=system platform=system.tsunami +min_backoff_delay=8 +max_backoff_delay=20000 configdata=system.tsunami.ide.configdata pci_bus=0 pci_dev=0 @@ -615,4 +625,5 @@ bus_id=0 clock=2 width=64 responder_set=true +block_size=64 diff --git a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt index 7947c3d76..466fb2d27 100644 --- a/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt +++ b/tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt @@ -1,84 +1,83 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 374146 # Simulator instruction rate (inst/s) -host_mem_usage 249416 # Number of bytes of host memory used -host_seconds 160.59 # Real time elapsed on the host -host_tick_rate 24179677 # Simulator tick rate (ticks/s) +host_inst_rate 233672 # Simulator instruction rate (inst/s) +host_seconds 257.14 # Real time elapsed on the host +host_tick_rate 15108417 # Simulator tick rate (ticks/s) sim_freq 2000000000 # Frequency of simulated ticks -sim_insts 60085523 # Number of instructions simulated -sim_seconds 1.941556 # Number of seconds simulated -sim_ticks 3883112324 # Number of ticks simulated -system.cpu.dtb.accesses 1020793 # DTB accesses +sim_insts 60085488 # Number of instructions simulated +sim_seconds 1.942464 # Number of seconds simulated +sim_ticks 3884928812 # Number of ticks simulated +system.cpu.dtb.accesses 1020784 # DTB accesses system.cpu.dtb.acv 367 # DTB access violations -system.cpu.dtb.hits 16070719 # DTB hits -system.cpu.dtb.misses 11472 # DTB misses -system.cpu.dtb.read_accesses 728862 # DTB read accesses +system.cpu.dtb.hits 16070353 # DTB hits +system.cpu.dtb.misses 11466 # DTB misses +system.cpu.dtb.read_accesses 728853 # DTB read accesses system.cpu.dtb.read_acv 210 # DTB read access violations -system.cpu.dtb.read_hits 9714788 # DTB read hits -system.cpu.dtb.read_misses 10330 # DTB read misses +system.cpu.dtb.read_hits 9714571 # DTB read hits +system.cpu.dtb.read_misses 10324 # DTB read misses system.cpu.dtb.write_accesses 291931 # DTB write accesses system.cpu.dtb.write_acv 157 # DTB write access violations -system.cpu.dtb.write_hits 6355931 # DTB write hits +system.cpu.dtb.write_hits 6355782 # DTB write hits system.cpu.dtb.write_misses 1142 # DTB write misses -system.cpu.idle_fraction 0.921464 # Percentage of idle cycles -system.cpu.itb.accesses 4985828 # ITB accesses +system.cpu.idle_fraction 0.921526 # Percentage of idle cycles +system.cpu.itb.accesses 4985698 # ITB accesses system.cpu.itb.acv 184 # ITB acv -system.cpu.itb.hits 4980818 # ITB hits +system.cpu.itb.hits 4980688 # ITB hits system.cpu.itb.misses 5010 # ITB misses -system.cpu.kern.callpal 193475 # number of callpals executed +system.cpu.kern.callpal 193483 # number of callpals executed system.cpu.kern.callpal_cserve 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrmces 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrfen 1 0.00% 0.00% # number of callpals executed system.cpu.kern.callpal_wrvptptr 1 0.00% 0.00% # number of callpals executed -system.cpu.kern.callpal_swpctx 4148 2.14% 2.15% # number of callpals executed +system.cpu.kern.callpal_swpctx 4144 2.14% 2.14% # number of callpals executed system.cpu.kern.callpal_tbi 54 0.03% 2.17% # number of callpals executed system.cpu.kern.callpal_wrent 7 0.00% 2.18% # number of callpals executed -system.cpu.kern.callpal_swpipl 176501 91.23% 93.40% # number of callpals executed -system.cpu.kern.callpal_rdps 6860 3.55% 96.95% # number of callpals executed +system.cpu.kern.callpal_swpipl 176511 91.23% 93.40% # number of callpals executed +system.cpu.kern.callpal_rdps 6861 3.55% 96.95% # number of callpals executed system.cpu.kern.callpal_wrkgp 1 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_wrusp 7 0.00% 96.95% # number of callpals executed system.cpu.kern.callpal_rdusp 9 0.00% 96.96% # number of callpals executed system.cpu.kern.callpal_whami 2 0.00% 96.96% # number of callpals executed -system.cpu.kern.callpal_rti 5186 2.68% 99.64% # number of callpals executed +system.cpu.kern.callpal_rti 5187 2.68% 99.64% # number of callpals executed system.cpu.kern.callpal_callsys 515 0.27% 99.91% # number of callpals executed system.cpu.kern.callpal_imb 181 0.09% 100.00% # number of callpals executed system.cpu.kern.inst.arm 0 # number of arm instructions executed -system.cpu.kern.inst.hwrei 212602 # number of hwrei instructions executed -system.cpu.kern.inst.quiesce 6154 # number of quiesce instructions executed -system.cpu.kern.ipl_count 183780 # number of times we switched to this ipl -system.cpu.kern.ipl_count_0 75067 40.85% 40.85% # number of times we switched to this ipl +system.cpu.kern.inst.hwrei 212605 # number of hwrei instructions executed +system.cpu.kern.inst.quiesce 6153 # number of quiesce instructions executed +system.cpu.kern.ipl_count 183792 # number of times we switched to this ipl +system.cpu.kern.ipl_count_0 75069 40.84% 40.84% # number of times we switched to this ipl system.cpu.kern.ipl_count_21 131 0.07% 40.92% # number of times we switched to this ipl -system.cpu.kern.ipl_count_22 1961 1.07% 41.98% # number of times we switched to this ipl -system.cpu.kern.ipl_count_31 106621 58.02% 100.00% # number of times we switched to this ipl -system.cpu.kern.ipl_good 149492 # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_0 73700 49.30% 49.30% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_count_22 1962 1.07% 41.98% # number of times we switched to this ipl +system.cpu.kern.ipl_count_31 106630 58.02% 100.00% # number of times we switched to this ipl +system.cpu.kern.ipl_good 149497 # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_0 73702 49.30% 49.30% # number of times we switched to this ipl from a different ipl system.cpu.kern.ipl_good_21 131 0.09% 49.39% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_22 1961 1.31% 50.70% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_good_31 73700 49.30% 100.00% # number of times we switched to this ipl from a different ipl -system.cpu.kern.ipl_ticks 3883110540 # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_0 3755984220 96.73% 96.73% # number of cycles we spent at this ipl +system.cpu.kern.ipl_good_22 1962 1.31% 50.70% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_good_31 73702 49.30% 100.00% # number of times we switched to this ipl from a different ipl +system.cpu.kern.ipl_ticks 3884927028 # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_0 3757863794 96.73% 96.73% # number of cycles we spent at this ipl system.cpu.kern.ipl_ticks_21 112456 0.00% 96.73% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_22 918754 0.02% 96.75% # number of cycles we spent at this ipl -system.cpu.kern.ipl_ticks_31 126095110 3.25% 100.00% # number of cycles we spent at this ipl -system.cpu.kern.ipl_used 0.813429 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.ipl_ticks_22 918216 0.02% 96.76% # number of cycles we spent at this ipl +system.cpu.kern.ipl_ticks_31 126032562 3.24% 100.00% # number of cycles we spent at this ipl +system.cpu.kern.ipl_used 0.813403 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_0 0.981790 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_21 1 # fraction of swpipl calls that actually changed the ipl system.cpu.kern.ipl_used_22 1 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.ipl_used_31 0.691233 # fraction of swpipl calls that actually changed the ipl -system.cpu.kern.mode_good_kernel 1897 +system.cpu.kern.ipl_used_31 0.691194 # fraction of swpipl calls that actually changed the ipl +system.cpu.kern.mode_good_kernel 1895 system.cpu.kern.mode_good_user 1742 -system.cpu.kern.mode_good_idle 155 +system.cpu.kern.mode_good_idle 153 system.cpu.kern.mode_switch_kernel 5935 # number of protection mode switches system.cpu.kern.mode_switch_user 1742 # number of protection mode switches -system.cpu.kern.mode_switch_idle 2065 # number of protection mode switches -system.cpu.kern.mode_switch_good 0.389448 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_kernel 0.319629 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_idle 2062 # number of protection mode switches +system.cpu.kern.mode_switch_good 0.389157 # fraction of useful protection mode switches +system.cpu.kern.mode_switch_good_kernel 0.319292 # fraction of useful protection mode switches system.cpu.kern.mode_switch_good_user 1 # fraction of useful protection mode switches -system.cpu.kern.mode_switch_good_idle 0.075061 # fraction of useful protection mode switches -system.cpu.kern.mode_ticks_kernel 112876118 2.91% 2.91% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_user 15210360 0.39% 3.30% # number of ticks spent at the given mode -system.cpu.kern.mode_ticks_idle 3755024054 96.70% 100.00% # number of ticks spent at the given mode -system.cpu.kern.swap_context 4149 # number of times the context was actually changed +system.cpu.kern.mode_switch_good_idle 0.074200 # fraction of useful protection mode switches +system.cpu.kern.mode_ticks_kernel 112890486 2.91% 2.91% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_user 15209884 0.39% 3.30% # number of ticks spent at the given mode +system.cpu.kern.mode_ticks_idle 3756826650 96.70% 100.00% # number of ticks spent at the given mode +system.cpu.kern.swap_context 4145 # number of times the context was actually changed system.cpu.kern.syscall 326 # number of syscalls executed system.cpu.kern.syscall_2 8 2.45% 2.45% # number of syscalls executed system.cpu.kern.syscall_3 30 9.20% 11.66% # number of syscalls executed @@ -110,10 +109,10 @@ system.cpu.kern.syscall_98 2 0.61% 97.55% # nu system.cpu.kern.syscall_132 4 1.23% 98.77% # number of syscalls executed system.cpu.kern.syscall_144 2 0.61% 99.39% # number of syscalls executed system.cpu.kern.syscall_147 2 0.61% 100.00% # number of syscalls executed -system.cpu.not_idle_fraction 0.078536 # Percentage of non-idle cycles -system.cpu.numCycles 3883112324 # number of cpu cycles simulated -system.cpu.num_insts 60085523 # Number of instructions executed -system.cpu.num_refs 16318655 # Number of memory references +system.cpu.not_idle_fraction 0.078474 # Percentage of non-idle cycles +system.cpu.numCycles 3884928812 # number of cpu cycles simulated +system.cpu.num_insts 60085488 # Number of instructions executed +system.cpu.num_refs 16318244 # Number of memory references system.disk0.dma_read_bytes 1024 # Number of bytes transfered via DMA reads (not PRD). system.disk0.dma_read_full_pages 0 # Number of full page size DMA reads (not PRD). system.disk0.dma_read_txs 1 # Number of DMA read transactions (not PRD). From 634d2e9d83054d2ddae4333d4e28e9a04cfbfd84 Mon Sep 17 00:00:00 2001 From: Ali Saidi Date: Thu, 10 May 2007 18:24:48 -0400 Subject: [PATCH 07/10] remove hit_latency and make latency do the right thing set the latency parameter in terms of a latency add caches to tsunami-simple configs configs/common/Caches.py: tests/configs/memtest.py: tests/configs/o3-timing-mp.py: tests/configs/o3-timing.py: tests/configs/simple-atomic-mp.py: tests/configs/simple-timing-mp.py: tests/configs/simple-timing.py: set the latency parameter in terms of a latency configs/common/FSConfig.py: give the bridge a default latency too src/mem/cache/cache_builder.cc: src/python/m5/objects/BaseCache.py: remove hit_latency and make latency do the right thing tests/configs/tsunami-simple-atomic-dual.py: tests/configs/tsunami-simple-atomic.py: tests/configs/tsunami-simple-timing-dual.py: tests/configs/tsunami-simple-timing.py: add caches to tsunami-simple configs --HG-- extra : convert_revision : 37bef7c652e97c8cdb91f471fba62978f89019f1 --- configs/common/Caches.py | 6 +-- configs/common/FSConfig.py | 4 +- src/mem/cache/cache_builder.cc | 6 +-- src/python/m5/objects/BaseCache.py | 3 +- tests/configs/memtest.py | 4 +- tests/configs/o3-timing-mp.py | 4 +- tests/configs/o3-timing.py | 2 +- tests/configs/simple-atomic-mp.py | 4 +- tests/configs/simple-timing-mp.py | 4 +- tests/configs/simple-timing.py | 4 +- tests/configs/tsunami-simple-atomic-dual.py | 43 ++++++++++++++++++-- tests/configs/tsunami-simple-atomic.py | 43 +++++++++++++++++++- tests/configs/tsunami-simple-timing-dual.py | 44 ++++++++++++++++++++- tests/configs/tsunami-simple-timing.py | 44 ++++++++++++++++++++- 14 files changed, 184 insertions(+), 31 deletions(-) diff --git a/configs/common/Caches.py b/configs/common/Caches.py index 4692ef537..4bff2c8a4 100644 --- a/configs/common/Caches.py +++ b/configs/common/Caches.py @@ -1,4 +1,4 @@ -# Copyright (c) 2006 The Regents of The University of Michigan +# Copyright (c) 2006-2007 The Regents of The University of Michigan # All rights reserved. # # Redistribution and use in source and binary forms, with or without @@ -32,7 +32,7 @@ from m5.objects import * class L1Cache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 protocol = CoherenceProtocol(protocol='moesi') @@ -40,7 +40,7 @@ class L1Cache(BaseCache): class L2Cache(BaseCache): assoc = 8 block_size = 64 - latency = 10 + latency = '10ns' mshrs = 20 tgts_per_mshr = 12 diff --git a/configs/common/FSConfig.py b/configs/common/FSConfig.py index 289a7a5f4..593baf169 100644 --- a/configs/common/FSConfig.py +++ b/configs/common/FSConfig.py @@ -61,7 +61,7 @@ def makeLinuxAlphaSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge(fix_partial_write_b=True) + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) self.bridge.side_a = self.iobus.port self.bridge.side_b = self.membus.port @@ -94,7 +94,7 @@ def makeSparcSystem(mem_mode, mdesc = None): self.readfile = mdesc.script() self.iobus = Bus(bus_id=0) self.membus = Bus(bus_id=1) - self.bridge = Bridge() + self.bridge = Bridge(fix_partial_write_b=True, delay='50ns', nack_delay='4ns') self.t1000 = T1000() self.t1000.attachOnChipIO(self.membus) self.t1000.attachIO(self.iobus) diff --git a/src/mem/cache/cache_builder.cc b/src/mem/cache/cache_builder.cc index 318b57d50..e887f711e 100644 --- a/src/mem/cache/cache_builder.cc +++ b/src/mem/cache/cache_builder.cc @@ -134,7 +134,6 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(BaseCache) Param prefetch_cache_check_push; Param prefetch_use_cpu_id; Param prefetch_data_accesses_only; - Param hit_latency; END_DECLARE_SIM_OBJECT_PARAMS(BaseCache) @@ -190,8 +189,7 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(BaseCache) INIT_PARAM_DFLT(prefetch_policy, "Type of prefetcher to use", "none"), INIT_PARAM_DFLT(prefetch_cache_check_push, "Check if in cash on push or pop of prefetch queue", true), INIT_PARAM_DFLT(prefetch_use_cpu_id, "Use the CPU ID to seperate calculations of prefetches", true), - INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false), - INIT_PARAM_DFLT(hit_latency, "Hit Latecny for a succesful access", 1) + INIT_PARAM_DFLT(prefetch_data_accesses_only, "Only prefetch on data not on instruction accesses", false) END_INIT_SIM_OBJECT_PARAMS(BaseCache) @@ -211,7 +209,7 @@ END_INIT_SIM_OBJECT_PARAMS(BaseCache) BUILD_NULL_PREFETCHER(TAGS); \ } \ Cache::Params params(tags, mq, coh, base_params, \ - pf, prefetch_access, hit_latency, \ + pf, prefetch_access, latency, \ true, \ store_compressed, \ adaptive_compression, \ diff --git a/src/python/m5/objects/BaseCache.py b/src/python/m5/objects/BaseCache.py index 773a11bea..7df5215e4 100644 --- a/src/python/m5/objects/BaseCache.py +++ b/src/python/m5/objects/BaseCache.py @@ -9,7 +9,7 @@ class BaseCache(MemObject): "Use an adaptive compression scheme") assoc = Param.Int("associativity") block_size = Param.Int("block size in bytes") - latency = Param.Int("Latency") + latency = Param.Latency("Latency") compressed_bus = Param.Bool(False, "This cache connects to a compressed memory") compression_latency = Param.Latency('0ns', @@ -59,6 +59,5 @@ class BaseCache(MemObject): "Use the CPU ID to seperate calculations of prefetches") prefetch_data_accesses_only = Param.Bool(False, "Only prefetch on data not on instruction accesses") - hit_latency = Param.Int(1,"Hit Latency of the cache") cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") diff --git a/tests/configs/memtest.py b/tests/configs/memtest.py index f56edef4a..15a4f8f05 100644 --- a/tests/configs/memtest.py +++ b/tests/configs/memtest.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 12 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 10 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing-mp.py b/tests/configs/o3-timing-mp.py index 1e414294c..1ac9bd2e4 100644 --- a/tests/configs/o3-timing-mp.py +++ b/tests/configs/o3-timing-mp.py @@ -35,7 +35,7 @@ m5.AddToPath('../configs/common') # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -47,7 +47,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/o3-timing.py b/tests/configs/o3-timing.py index d20a7e0c8..366a3eb0d 100644 --- a/tests/configs/o3-timing.py +++ b/tests/configs/o3-timing.py @@ -33,7 +33,7 @@ m5.AddToPath('../configs/common') class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 diff --git a/tests/configs/simple-atomic-mp.py b/tests/configs/simple-atomic-mp.py index e8000cd0a..de0793d1c 100644 --- a/tests/configs/simple-atomic-mp.py +++ b/tests/configs/simple-atomic-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing-mp.py b/tests/configs/simple-timing-mp.py index a263bcf57..1fd0e8c3c 100644 --- a/tests/configs/simple-timing-mp.py +++ b/tests/configs/simple-timing-mp.py @@ -34,7 +34,7 @@ from m5.objects import * # ==================== class L1(BaseCache): - latency = 1 + latency = '1ns' block_size = 64 mshrs = 4 tgts_per_mshr = 8 @@ -46,7 +46,7 @@ class L1(BaseCache): class L2(BaseCache): block_size = 64 - latency = 100 + latency = '10ns' mshrs = 92 tgts_per_mshr = 16 write_buffers = 8 diff --git a/tests/configs/simple-timing.py b/tests/configs/simple-timing.py index 6c4b8232f..0ed985a17 100644 --- a/tests/configs/simple-timing.py +++ b/tests/configs/simple-timing.py @@ -32,13 +32,13 @@ from m5.objects import * class MyCache(BaseCache): assoc = 2 block_size = 64 - latency = 1 + latency = '1ns' mshrs = 10 tgts_per_mshr = 5 cpu = TimingSimpleCPU(cpu_id=0) cpu.addTwoLevelCacheHierarchy(MyCache(size = '128kB'), MyCache(size = '256kB'), - MyCache(size = '2MB')) + MyCache(size = '2MB', latency='10ns')) system = System(cpu = cpu, physmem = PhysicalMemory(), membus = Bus()) diff --git a/tests/configs/tsunami-simple-atomic-dual.py b/tests/configs/tsunami-simple-atomic-dual.py index 7ed854f44..131095055 100644 --- a/tests/configs/tsunami-simple-atomic-dual.py +++ b/tests/configs/tsunami-simple-atomic-dual.py @@ -31,12 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ AtomicSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) - -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') diff --git a/tests/configs/tsunami-simple-atomic.py b/tests/configs/tsunami-simple-atomic.py index 4859f30cf..595b1aeda 100644 --- a/tests/configs/tsunami-simple-atomic.py +++ b/tests/configs/tsunami-simple-atomic.py @@ -31,10 +31,49 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = AtomicSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('atomic') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + diff --git a/tests/configs/tsunami-simple-timing-dual.py b/tests/configs/tsunami-simple-timing-dual.py index 0c8c3d523..47fba30ff 100644 --- a/tests/configs/tsunami-simple-timing-dual.py +++ b/tests/configs/tsunami-simple-timing-dual.py @@ -31,11 +31,51 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(2) ] +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpus +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s for c in cpus: - c.connectMemPorts(system.membus) + c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) + # connect cpu level-1 caches to shared level-2 cache + c.connectMemPorts(system.toL2Bus) + c.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + + diff --git a/tests/configs/tsunami-simple-timing.py b/tests/configs/tsunami-simple-timing.py index 9f532e3ae..999bde087 100644 --- a/tests/configs/tsunami-simple-timing.py +++ b/tests/configs/tsunami-simple-timing.py @@ -31,10 +31,50 @@ from m5.objects import * m5.AddToPath('../configs/common') import FSConfig + +# -------------------- +# Base L1 Cache +# ==================== + +class L1(BaseCache): + latency = '1ns' + block_size = 64 + mshrs = 4 + tgts_per_mshr = 8 + protocol = CoherenceProtocol(protocol='moesi') + +# ---------------------- +# Base L2 Cache +# ---------------------- + +class L2(BaseCache): + block_size = 64 + latency = '10ns' + mshrs = 92 + tgts_per_mshr = 16 + write_buffers = 8 + +#cpu cpu = TimingSimpleCPU(cpu_id=0) +#the system system = FSConfig.makeLinuxAlphaSystem('timing') + system.cpu = cpu -cpu.connectMemPorts(system.membus) +#create the l1/l2 bus +system.toL2Bus = Bus() + +#connect up the l2 cache +system.l2c = L2(size='4MB', assoc=8) +system.l2c.cpu_side = system.toL2Bus.port +system.l2c.mem_side = system.membus.port + +#connect up the cpu and l1s +cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), + L1(size = '32kB', assoc = 4)) +# connect cpu level-1 caches to shared level-2 cache +cpu.connectMemPorts(system.toL2Bus) +cpu.clock = '2GHz' root = Root(system=system) -m5.ticks.setGlobalFrequency('2GHz') +m5.ticks.setGlobalFrequency('1THz') + From d667ce01b488e505569d6dce253f97e4246851cf Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:47:18 -0700 Subject: [PATCH 08/10] total should be the sum of the vector result of an operation, not sum the operands and then apply the operation. --HG-- extra : convert_revision : 06486e59b3dd9588b458ef45c341cc4f2554dc09 --- src/base/statistics.hh | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/src/base/statistics.hh b/src/base/statistics.hh index 761b30c2b..8d3f53d4c 100644 --- a/src/base/statistics.hh +++ b/src/base/statistics.hh @@ -2094,9 +2094,13 @@ class UnaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { return l->size(); } @@ -2149,9 +2153,13 @@ class BinaryNode : public Node return vresult; } - Result total() const { - Op op; - return op(l->total(), r->total()); + Result total() const + { + const VResult &vec = this->result(); + Result total = 0; + for (int i = 0; i < size(); i++) + total += vec[i]; + return total; } virtual size_t size() const { From 113319a7da9fe442f4f765b76c5728974824f2cc Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 11:48:58 -0700 Subject: [PATCH 09/10] Float should have a c++ param type --HG-- extra : convert_revision : 150bbe7f31aafb43a75195fc2a365fb3c0ec5673 --- src/python/m5/params.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/python/m5/params.py b/src/python/m5/params.py index da7ddd65e..88b162874 100644 --- a/src/python/m5/params.py +++ b/src/python/m5/params.py @@ -348,7 +348,7 @@ class UdpPort(CheckedInt): cxx_type = 'uint16_t'; size = 16; unsigned = True class Percent(CheckedInt): cxx_type = 'int'; min = 0; max = 100 class Float(ParamValue, float): - pass + cxx_type = 'double' class MemorySize(CheckedInt): cxx_type = 'uint64_t' From 011db5c8515804145202373440bad26fa21b30a7 Mon Sep 17 00:00:00 2001 From: Nathan Binkert Date: Fri, 11 May 2007 15:01:44 -0700 Subject: [PATCH 10/10] Move full CPU sim object stuff into the encumbered directory --HG-- extra : convert_revision : 788068dd4f4994d0016dba7e8705359d45a3a45c --- src/python/SConscript | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/python/SConscript b/src/python/SConscript index 3c5ab4da1..562278aa0 100644 --- a/src/python/SConscript +++ b/src/python/SConscript @@ -81,7 +81,6 @@ SimObject('m5/objects/Ethernet.py') SimObject('m5/objects/FUPool.py') SimObject('m5/objects/FastCPU.py') #SimObject('m5/objects/FreebsdSystem.py') -SimObject('m5/objects/FullCPU.py') SimObject('m5/objects/FuncUnit.py') SimObject('m5/objects/FuncUnitConfig.py') SimObject('m5/objects/FunctionalMemory.py') @@ -97,7 +96,6 @@ SimObject('m5/objects/O3CPU.py') SimObject('m5/objects/OzoneCPU.py') SimObject('m5/objects/Pci.py') SimObject('m5/objects/PhysicalMemory.py') -SimObject('m5/objects/PipeTrace.py') SimObject('m5/objects/Platform.py') SimObject('m5/objects/Process.py') SimObject('m5/objects/Repl.py')