cleanup interrupt code for gigabit device
dev/ns_gige.cc:
Clean up the interrupt code. Do a better job determining when
coalescing should happen.
Remove some bogus comments
Stop using magic numbers in initialization and comment what
the various numbers do
dev/ns_gige_reg.h:
#define describing which interrupts cannot be delayed and
which interrrupts we don't implement
--HG--
extra : convert_revision : eb196afa0bf448e1849dd2bd30dde32134effee7
This commit is contained in:
Nathan Binkert
parent
256afbbe26
commit
40174f119d
2 changed files with 32 additions and 130 deletions
149
dev/ns_gige.cc
149
dev/ns_gige.cc
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@ -925,74 +925,25 @@ NSGigE::write(MemReqPtr &req, const uint8_t *data)
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void
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NSGigE::devIntrPost(uint32_t interrupts)
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{
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bool delay = false;
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if (interrupts & ISR_RESERVE)
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panic("Cannot set a reserved interrupt");
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if (interrupts & ISR_TXRCMP)
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regs.isr |= ISR_TXRCMP;
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if (interrupts & ISR_NOIMPL)
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warn("interrupt not implemented %#x\n", interrupts);
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if (interrupts & ISR_RXRCMP)
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regs.isr |= ISR_RXRCMP;
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//ISR_DPERR not implemented
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//ISR_SSERR not implemented
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//ISR_RMABT not implemented
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//ISR_RXSOVR not implemented
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//ISR_HIBINT not implemented
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//ISR_PHY not implemented
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//ISR_PME not implemented
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if (interrupts & ISR_SWI)
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regs.isr |= ISR_SWI;
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//ISR_MIB not implemented
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//ISR_TXURN not implemented
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if (interrupts & ISR_TXIDLE)
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regs.isr |= ISR_TXIDLE;
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if (interrupts & ISR_TXERR)
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regs.isr |= ISR_TXERR;
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if (interrupts & ISR_TXDESC)
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regs.isr |= ISR_TXDESC;
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if (interrupts & ISR_TXOK) {
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regs.isr |= ISR_TXOK;
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delay = true;
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}
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if (interrupts & ISR_RXORN)
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regs.isr |= ISR_RXORN;
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if (interrupts & ISR_RXIDLE)
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regs.isr |= ISR_RXIDLE;
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//ISR_RXEARLY not implemented
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if (interrupts & ISR_RXERR)
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regs.isr |= ISR_RXERR;
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if (interrupts & ISR_RXDESC)
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regs.isr |= ISR_RXDESC;
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if (interrupts & ISR_RXOK) {
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delay = true;
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regs.isr |= ISR_RXOK;
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}
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if ((regs.isr & regs.imr)) {
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Tick when = curTick;
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if (delay)
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when += intrDelay;
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cpuIntrPost(when);
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}
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interrupts &= ~ISR_NOIMPL;
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regs.isr |= interrupts;
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DPRINTF(EthernetIntr,
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"interrupt written to ISR: intr=%#x isr=%#x imr=%#x\n",
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interrupts, regs.isr, regs.imr);
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if ((regs.isr & regs.imr)) {
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Tick when = curTick;
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if (!(regs.isr & regs.imr & ISR_NODELAY))
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when += intrDelay;
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cpuIntrPost(when);
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}
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}
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void
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@ -1001,54 +952,8 @@ NSGigE::devIntrClear(uint32_t interrupts)
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if (interrupts & ISR_RESERVE)
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panic("Cannot clear a reserved interrupt");
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if (interrupts & ISR_TXRCMP)
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regs.isr &= ~ISR_TXRCMP;
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if (interrupts & ISR_RXRCMP)
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regs.isr &= ~ISR_RXRCMP;
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//ISR_DPERR not implemented
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//ISR_SSERR not implemented
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//ISR_RMABT not implemented
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//ISR_RXSOVR not implemented
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//ISR_HIBINT not implemented
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//ISR_PHY not implemented
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//ISR_PME not implemented
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if (interrupts & ISR_SWI)
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regs.isr &= ~ISR_SWI;
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//ISR_MIB not implemented
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//ISR_TXURN not implemented
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if (interrupts & ISR_TXIDLE)
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regs.isr &= ~ISR_TXIDLE;
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if (interrupts & ISR_TXERR)
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regs.isr &= ~ISR_TXERR;
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if (interrupts & ISR_TXDESC)
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regs.isr &= ~ISR_TXDESC;
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if (interrupts & ISR_TXOK)
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regs.isr &= ~ISR_TXOK;
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if (interrupts & ISR_RXORN)
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regs.isr &= ~ISR_RXORN;
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if (interrupts & ISR_RXIDLE)
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regs.isr &= ~ISR_RXIDLE;
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//ISR_RXEARLY not implemented
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if (interrupts & ISR_RXERR)
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regs.isr &= ~ISR_RXERR;
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if (interrupts & ISR_RXDESC)
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regs.isr &= ~ISR_RXDESC;
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if (interrupts & ISR_RXOK)
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regs.isr &= ~ISR_RXOK;
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interrupts &= ~ISR_NOIMPL;
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regs.isr &= ~interrupts;
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DPRINTF(EthernetIntr,
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"interrupt cleared from ISR: intr=%x isr=%x imr=%x\n",
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@ -1134,9 +1039,8 @@ NSGigE::cpuInterrupt()
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// Send interrupt
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cpuPendingIntr = true;
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/** @todo rework the intctrl to be tsunami ok */
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//intctrl->post(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
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DPRINTF(EthernetIntr, "Posting interrupts to cchip!\n");
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DPRINTF(EthernetIntr, "posting cchip interrupt\n");
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tsunami->cchip->postDRIR(configData->config.hdr.pci0.interruptLine);
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}
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@ -1147,9 +1051,8 @@ NSGigE::cpuIntrClear()
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return;
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cpuPendingIntr = false;
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/** @todo rework the intctrl to be tsunami ok */
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//intctrl->clear(TheISA::INTLEVEL_IRQ1, TheISA::INTINDEX_ETHERNET);
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DPRINTF(EthernetIntr, "clearing all interrupts from cchip\n");
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DPRINTF(EthernetIntr, "clearing cchip interrupt\n");
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tsunami->cchip->clearDRIR(configData->config.hdr.pci0.interruptLine);
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}
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@ -1193,15 +1096,15 @@ void
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NSGigE::regsReset()
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{
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memset(®s, 0, sizeof(regs));
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regs.config = 0x80000000;
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regs.mear = 0x12;
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regs.isr = 0x00608000;
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regs.txcfg = 0x120;
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regs.rxcfg = 0x4;
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regs.srr = 0x0103;
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regs.mibc = 0x2;
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regs.vdr = 0x81;
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regs.tesr = 0xc000;
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regs.config = CFG_LNKSTS;
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regs.mear = MEAR_MDDIR | MEAR_EEDO;
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regs.txcfg = 0x120; // set drain threshold to 1024 bytes and
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// fill threshold to 32 bytes
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regs.rxcfg = 0x4; // set drain threshold to 16 bytes
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regs.srr = 0x0103; // set the silicon revision to rev B or 0x103
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regs.mibc = MIBC_FRZ;
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regs.vdr = 0x81; // set the vlan tag type to 802.1q
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regs.tesr = 0xc000; // TBI capable of both full and half duplex
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extstsEnable = false;
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acceptBroadcast = false;
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@ -55,17 +55,13 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* @file
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* Ethernet device register definitions for the National
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* Semiconductor DP83820 Ethernet controller
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*/
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#ifndef _NS_GIGE_H
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#define _NS_GIGE_H_
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#ifndef __DEV_NS_GIGE_REG_H__
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#define __DEV_NS_GIGE_REG_H__
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/*
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* Configuration Register Map
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@ -220,6 +216,9 @@
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#define ISR_RXDESC 0x00000002
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#define ISR_RXOK 0x00000001
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#define ISR_ALL 0x7FFFFFFF
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#define ISR_NODELAY (ISR_ALL & ~(ISR_RXOK|ISR_RXDESC|ISR_TXOK|ISR_TXDESC))
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#define ISR_NOIMPL (~(ISR_SWI|ISR_TXIDLE|ISR_TXDESC|ISR_TXOK|ISR_RXORN| \
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ISR_RXIDLE|ISR_RXDESC|ISR_RXOK))
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/* transmit configuration register */
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#define TXCFG_CSI 0x80000000
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@ -369,4 +368,4 @@ struct ns_desc {
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/* speed status */
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#define SPDSTS_POLARITY (CFG_SPDSTS1 | CFG_SPDSTS0 | CFG_DUPSTS | (lnksts ? CFG_LNKSTS : 0))
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#endif /* _NS_GIGE_H_ */
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#endif /* __DEV_NS_GIGE_REG_H__ */
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