sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Support new flags now used instead of flags in decoder.isa.

Browse source 
cpu/ozone/front_end_impl.hh:
cpu/ozone/lw_back_end_impl.hh:
cpu/ozone/lw_lsq_impl.hh:
    Support new flags added in.

--HG--
extra : convert_revision : 2e756fd1913cf600650afc39dd715d59b9b89c42
This commit is contained in:
Kevin Lim 2006-05-24 14:31:06 -04:00
parent 16df8221ff
commit 3fe3523232
3 changed files with 18 additions and 11 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
cpu/ozone/front_end_impl.hh
View file

@ -503,11 +503,14 @@ FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
if (serializeNext) { if (serializeNext) {
inst->setSerializeBefore(); inst->setSerializeBefore();
serializeNext = false; serializeNext = false;
} else if (!inst->isSerializing()) { } else if (!inst->isSerializing() &&
!inst->isIprAccess() &&
!inst->isStoreConditional()) {
return false; return false;
} }
if (inst->isSerializeBefore() && !inst->isSerializeHandled()) { if ((inst->isIprAccess() || inst->isSerializeBefore()) &&
!inst->isSerializeHandled()) {
DPRINTF(FE, "Serialize before instruction encountered.\n"); DPRINTF(FE, "Serialize before instruction encountered.\n");
if (!inst->isTempSerializeBefore()) { if (!inst->isTempSerializeBefore()) {
@ -523,7 +526,8 @@ FrontEnd<Impl>::processBarriers(DynInstPtr &inst)
barrierInst = inst; barrierInst = inst;
return true; return true;
} else if (inst->isSerializeAfter() && !inst->isSerializeHandled()) { } else if ((inst->isStoreConditional() || inst->isSerializeAfter())
&& !inst->isSerializeHandled()) {
DPRINTF(FE, "Serialize after instruction encountered.\n"); DPRINTF(FE, "Serialize after instruction encountered.\n");
inst->setSerializeHandled(); inst->setSerializeHandled();

12
cpu/ozone/lw_back_end_impl.hh
View file

@ -66,8 +66,9 @@ LWBackEnd<Impl>::wakeDependents(DynInstPtr &inst, bool memory_deps)
DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum); DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
if (dep_inst->readyToIssue() && dep_inst->isInROB() && if (dep_inst->readyToIssue() && dep_inst->isInROB() &&
!dep_inst->isNonSpeculative() && !dep_inst->isNonSpeculative() && !dep_inst->isStoreConditional() &&
dep_inst->memDepReady() && !dep_inst->isMemBarrier() && !dep_inst->isWriteBarrier()) { dep_inst->memDepReady() && !dep_inst->isMemBarrier() &&
!dep_inst->isWriteBarrier()) {
DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n", DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n",
dep_inst->seqNum); dep_inst->seqNum);
exeList.push(dep_inst); exeList.push(dep_inst);
@ -768,7 +769,9 @@ LWBackEnd<Impl>::dispatchInsts()
} }
memBarrier = inst; memBarrier = inst;
inst->setCanCommit(); inst->setCanCommit();
} else if (inst->readyToIssue() && !inst->isNonSpeculative()) { } else if (inst->readyToIssue() &&
!inst->isNonSpeculative() &&
!inst->isStoreConditional()) {
if (inst->isMemRef()) { if (inst->isMemRef()) {
LSQ.insert(inst); LSQ.insert(inst);
@ -803,7 +806,7 @@ LWBackEnd<Impl>::dispatchInsts()
exeList.push(inst); exeList.push(inst);
} }
} else { } else {
if (inst->isNonSpeculative()) { if (inst->isNonSpeculative() || inst->isStoreConditional()) {
inst->setCanCommit(); inst->setCanCommit();
DPRINTF(BE, "Adding non speculative instruction\n"); DPRINTF(BE, "Adding non speculative instruction\n");
} }
@ -1079,6 +1082,7 @@ LWBackEnd<Impl>::commitInst(int inst_num)
// or store inst. Signal backwards that it should be executed. // or store inst. Signal backwards that it should be executed.
if (!inst->isExecuted()) { if (!inst->isExecuted()) {
if (inst->isNonSpeculative() || if (inst->isNonSpeculative() ||
inst->isStoreConditional() ||
inst->isMemBarrier() || inst->isMemBarrier() ||
inst->isWriteBarrier()) { inst->isWriteBarrier()) {
#if !FULL_SYSTEM #if !FULL_SYSTEM

7
cpu/ozone/lw_lsq_impl.hh
View file

@ -364,10 +364,9 @@ OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
if (store_fault != NoFault) { if (store_fault != NoFault) {
panic("Fault in a store instruction!"); panic("Fault in a store instruction!");
storeFaultInst = store_inst; storeFaultInst = store_inst;
} else if (store_inst->isNonSpeculative()) { } else if (store_inst->isStoreConditional()) {
// Nonspeculative accesses (namely store conditionals) // Store conditionals need to set themselves as able to
// need to set themselves as able to writeback if we // writeback if we haven't had a fault by here.
// haven't had a fault by here.
(*sq_it).canWB = true; (*sq_it).canWB = true;
++storesToWB; ++storesToWB;