sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Configs: SE script fix for Alpha and Ruby simulations

Browse source 
PIO interrupt port is only present for x86. Do not attempt to connect
for other ISAs.
This commit is contained in:
Malek Musleh 2012-09-28 09:35:25 -04:00
parent 6596059d05
commit 3fc23b9b96
1 changed files with 5 additions and 3 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

8
configs/example/se.py
View file

@ -190,15 +190,17 @@ if options.ruby:
ruby_port = system.ruby._cpu_ruby_ports[i] ruby_port = system.ruby._cpu_ruby_ports[i]
# Create the interrupt controller and connect its ports to Ruby # Create the interrupt controller and connect its ports to Ruby
# Note that the interrupt controller is always present but only
# in x86 does it have message ports that need to be connected
system.cpu[i].createInterruptController() system.cpu[i].createInterruptController()
system.cpu[i].interrupts.pio = ruby_port.master
system.cpu[i].interrupts.int_master = ruby_port.slave
system.cpu[i].interrupts.int_slave = ruby_port.master
# Connect the cpu's cache ports to Ruby # Connect the cpu's cache ports to Ruby
system.cpu[i].icache_port = ruby_port.slave system.cpu[i].icache_port = ruby_port.slave
system.cpu[i].dcache_port = ruby_port.slave system.cpu[i].dcache_port = ruby_port.slave
if buildEnv['TARGET_ISA'] == 'x86': if buildEnv['TARGET_ISA'] == 'x86':
system.cpu[i].interrupts.pio = ruby_port.master
system.cpu[i].interrupts.int_master = ruby_port.slave
system.cpu[i].interrupts.int_slave = ruby_port.master
system.cpu[i].itb.walker.port = ruby_port.slave system.cpu[i].itb.walker.port = ruby_port.slave
system.cpu[i].dtb.walker.port = ruby_port.slave system.cpu[i].dtb.walker.port = ruby_port.slave
else: else: