Made Addr a global type
--HG-- extra : convert_revision : 869bd9fa5d8591115ac9b4a7401eb2490986b835
This commit is contained in:
parent
74d7cd1cea
commit
3f7979c99d
50 changed files with 58 additions and 143 deletions
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@ -42,7 +42,6 @@ class ExecContext;
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class AlphaTLB : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef std::multimap<Addr, int> PageTable;
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PageTable lookupTable; // Quick lookup into page table
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@ -83,7 +82,6 @@ class AlphaTLB : public SimObject
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class AlphaITB : public AlphaTLB
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{
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protected:
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typedef TheISA::Addr Addr;
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mutable Stats::Scalar<> hits;
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mutable Stats::Scalar<> misses;
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mutable Stats::Scalar<> acv;
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@ -34,14 +34,12 @@
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class AlphaFault : public Fault
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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AlphaFault(char * newName, int newId, Addr newVect)
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: Fault(newName, newId), vect(newVect)
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{;}
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TheISA::Addr vect;
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Addr vect;
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};
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extern class ResetFaultType : public AlphaFault
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@ -39,8 +39,6 @@ output header {{
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*/
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class PCDependentDisassembly : public AlphaStaticInst
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{
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protected:
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typedef TheISA::Addr Addr;
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protected:
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/// Cached program counter from last disassembly
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mutable Addr cachedPC;
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@ -66,7 +64,6 @@ output header {{
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class Branch : public PCDependentDisassembly
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{
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protected:
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typedef TheISA::Addr Addr;
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/// Displacement to target address (signed).
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int32_t disp;
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@ -90,7 +87,6 @@ output header {{
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class Jump : public PCDependentDisassembly
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{
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protected:
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typedef TheISA::Addr Addr;
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/// Displacement to target address (signed).
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int32_t disp;
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@ -56,7 +56,7 @@ namespace AlphaISA
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{
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typedef uint32_t MachInst;
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typedef uint64_t Addr;
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// typedef uint64_t Addr;
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typedef uint8_t RegIndex;
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enum {
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@ -37,8 +37,6 @@ class StackTrace;
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class ProcessInfo
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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ExecContext *xc;
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@ -59,7 +57,6 @@ class ProcessInfo
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class StackTrace
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef TheISA::MachInst MachInst;
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private:
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ExecContext *xc;
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@ -35,16 +35,16 @@ class ExecContext;
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class PhysicalMemory;
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AlphaISA::PageTableEntry
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kernel_pte_lookup(PhysicalMemory *pmem, AlphaISA::Addr ptbr, AlphaISA::VAddr vaddr);
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kernel_pte_lookup(PhysicalMemory *pmem, Addr ptbr, AlphaISA::VAddr vaddr);
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AlphaISA::Addr vtophys(PhysicalMemory *xc, AlphaISA::Addr vaddr);
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AlphaISA::Addr vtophys(ExecContext *xc, AlphaISA::Addr vaddr);
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uint8_t *vtomem(ExecContext *xc, AlphaISA::Addr vaddr, size_t len);
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uint8_t *ptomem(ExecContext *xc, AlphaISA::Addr paddr, size_t len);
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Addr vtophys(PhysicalMemory *xc, Addr vaddr);
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Addr vtophys(ExecContext *xc, Addr vaddr);
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uint8_t *vtomem(ExecContext *xc, Addr vaddr, size_t len);
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uint8_t *ptomem(ExecContext *xc, Addr paddr, size_t len);
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void CopyOut(ExecContext *xc, void *dst, AlphaISA::Addr src, size_t len);
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void CopyIn(ExecContext *xc, AlphaISA::Addr dst, void *src, size_t len);
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void CopyString(ExecContext *xc, char *dst, AlphaISA::Addr vaddr, size_t maxlen);
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void CopyOut(ExecContext *xc, void *dst, Addr src, size_t len);
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void CopyIn(ExecContext *xc, Addr dst, void *src, size_t len);
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void CopyString(ExecContext *xc, char *dst, Addr vaddr, size_t maxlen);
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#endif // __ARCH_ALPHA_VTOPHYS_H__
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@ -37,7 +37,6 @@ class SymbolTable;
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class ObjectFile
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{
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public:
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typedef TheISA::Addr Addr;
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enum Arch {
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UnknownArch,
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@ -37,9 +37,8 @@
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class Checkpoint;
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class SymbolTable
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{
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typedef TheISA::Addr Addr;
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public:
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typedef std::map<TheISA::Addr, std::string> ATable;
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typedef std::map<Addr, std::string> ATable;
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typedef std::map<std::string, Addr> STable;
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private:
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@ -44,7 +44,6 @@ class GDBListener;
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class RemoteGDB
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef TheISA::MachInst MachInst;
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private:
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friend void debugger();
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@ -48,7 +48,6 @@ class ExecContext;
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class BaseCPU : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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// CPU's clock period in terms of the number of ticks of curTime.
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Tick clock;
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@ -62,8 +62,6 @@ class BaseDynInst : public FastAlloc, public RefCounted
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/// Binary machine instruction type.
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typedef TheISA::MachInst MachInst;
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/// Memory address type.
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typedef TheISA::Addr Addr;
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/// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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/// Integer register index type.
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@ -69,7 +69,6 @@ class ExecContext
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{
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protected:
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typedef TheISA::RegFile RegFile;
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typedef TheISA::Addr Addr;
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typedef TheISA::MachInst MachInst;
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typedef TheISA::MiscRegFile MiscRegFile;
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public:
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@ -46,7 +46,6 @@ namespace Trace {
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class InstRecord : public Record
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef TheISA::IntRegFile IntRegFile;
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// The following fields are initialized by the constructor and
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@ -172,7 +171,7 @@ inline
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InstRecord *
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getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
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const StaticInstPtr staticInst,
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TheISA::Addr pc, int thread = 0)
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Addr pc, int thread = 0)
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{
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if (DTRACE(InstExec) &&
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(InstRecord::traceMisspec() || !xc->misspeculating())) {
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@ -42,8 +42,6 @@
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class ExecContext;
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class MemTest : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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MemTest(const std::string &name,
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@ -35,8 +35,6 @@
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class DefaultBP
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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/**
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* Default branch predictor constructor.
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@ -40,7 +40,6 @@ template <class Impl>
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class AlphaFullCPU : public FullO3CPU<Impl>
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{
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protected:
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typedef AlphaISA::Addr Addr;
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typedef TheISA::IntReg IntReg;
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public:
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typedef typename Impl::Params Params;
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@ -50,8 +50,6 @@ class AlphaDynInst : public BaseDynInst<Impl>
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/** Binary machine instruction type. */
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typedef TheISA::MachInst MachInst;
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/** Memory address type. */
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typedef TheISA::Addr Addr;
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/** Logical register index type. */
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typedef TheISA::RegIndex RegIndex;
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/** Integer register index type. */
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@ -53,8 +53,6 @@
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template<class Impl>
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class TwobitBPredUnit
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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typedef typename Impl::Params Params;
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typedef typename Impl::DynInstPtr DynInstPtr;
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@ -34,8 +34,6 @@
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class DefaultBTB
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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struct BTBEntry
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{
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@ -49,9 +49,6 @@ class SimpleDecode
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typedef typename CPUPol::DecodeStruct DecodeStruct;
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typedef typename CPUPol::TimeStruct TimeStruct;
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// Typedefs from the ISA.
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typedef TheISA::Addr Addr;
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public:
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// The only time decode will become blocked is if dispatch becomes
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// blocked, which means IQ or ROB is probably full.
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@ -61,7 +61,6 @@ class SimpleFetch
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/** Typedefs from ISA. */
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typedef TheISA::MachInst MachInst;
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typedef TheISA::Addr Addr;
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public:
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enum Status {
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@ -34,8 +34,6 @@
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class ReturnAddrStack
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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ReturnAddrStack(unsigned numEntries);
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@ -53,7 +53,6 @@ template <class Impl>
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class PhysRegFile
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef TheISA::IntReg IntReg;
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typedef TheISA::FloatReg FloatReg;
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typedef TheISA::MiscRegFile MiscRegFile;
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@ -61,7 +61,6 @@ class SimpleRename
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typedef typename CPUPol::RenameMap RenameMap;
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// Typedefs from the ISA.
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typedef TheISA::Addr Addr;
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typedef TheISA::RegIndex RegIndex;
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public:
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@ -36,8 +36,6 @@
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class StoreSet
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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typedef unsigned SSID;
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@ -35,8 +35,6 @@
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class TournamentBP
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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/**
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* Default branch predictor constructor.
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@ -136,14 +136,14 @@ BreakPCEvent::process(ExecContext *xc)
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#if FULL_SYSTEM
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extern "C"
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void
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sched_break_pc_sys(System *sys, TheISA::Addr addr)
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sched_break_pc_sys(System *sys, Addr addr)
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{
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new BreakPCEvent(&sys->pcEventQueue, "debug break", addr, true);
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}
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extern "C"
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void
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sched_break_pc(TheISA::Addr addr)
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sched_break_pc(Addr addr)
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{
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for (vector<System *>::iterator sysi = System::systemList.begin();
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sysi != System::systemList.end(); ++sysi) {
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@ -39,7 +39,6 @@ class PCEventQueue;
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class PCEvent
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{
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protected:
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typedef TheISA::Addr Addr;
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static const Addr badpc = MemReq::inval_addr;
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protected:
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@ -65,7 +64,6 @@ class PCEvent
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class PCEventQueue
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{
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protected:
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typedef TheISA::Addr Addr;
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typedef PCEvent * record_t;
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class MapCompare {
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public:
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class BreakPCEvent : public PCEvent
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{
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protected:
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typedef TheISA::Addr Addr;
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bool remove;
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public:
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@ -37,8 +37,6 @@
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class ProfileNode
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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friend class FunctionProfile;
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@ -59,8 +57,6 @@ class ProfileNode
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class Callback;
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class FunctionProfile
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{
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public:
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typedef TheISA::Addr Addr;
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private:
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Callback *reset;
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const SymbolTable *symtab;
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@ -229,8 +229,6 @@ class StaticInst : public StaticInstBase
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/// Binary machine instruction type.
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typedef TheISA::MachInst MachInst;
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/// Memory address type.
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typedef TheISA::Addr Addr;
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/// Logical register index type.
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typedef TheISA::RegIndex RegIndex;
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@ -49,8 +49,6 @@ class MemTraceReader;
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*/
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class OptCPU : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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typedef int RefIndex;
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@ -46,8 +46,6 @@
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*/
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class ITXReader : public MemTraceReader
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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/** Trace file. */
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FILE *trace;
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@ -187,8 +187,6 @@ class IdeController;
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*/
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class IdeDisk : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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protected:
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/** The IDE controller for this disk. */
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IdeController *ctrl;
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@ -53,8 +53,6 @@ class MemoryController;
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*/
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class PciConfigData : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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/**
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* Constructor to initialize the devices config space to 0.
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@ -44,8 +44,6 @@ class Uart;
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class Platform : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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/** Pointer to the interrupt controller */
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IntrControl *intrctrl;
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@ -44,8 +44,6 @@ class PhysicalMemory;
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*/
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class SimpleDisk : public SimObject
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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typedef uint64_t baddr_t;
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@ -163,7 +163,7 @@ struct Info
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/* namespace Regs */ }
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inline const Regs::Info&
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regInfo(TheISA::Addr daddr)
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regInfo(Addr daddr)
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{
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static Regs::Info invalid = { 0, false, false, "invalid" };
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static Regs::Info info [] = {
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@ -199,7 +199,7 @@ regInfo(TheISA::Addr daddr)
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}
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inline bool
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regValid(TheISA::Addr daddr)
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regValid(Addr daddr)
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{
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if (daddr > Regs::Size)
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return false;
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@ -55,8 +55,6 @@ class System;
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class Tsunami : public Platform
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{
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protected:
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typedef TheISA::Addr Addr;
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public:
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/** Max number of CPUs in a Tsunami */
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static const int Max_CPUs = 64;
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@ -50,8 +50,6 @@ extern const char *modestr[];
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class Binning
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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std::string myname;
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System *system;
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@ -126,8 +124,6 @@ class Binning
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class Statistics : public Serializable
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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friend class Binning;
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@ -37,7 +37,7 @@
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#if __GNUC__ == 3 && __GNUC_MINOR__ != 3
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typedef uint64_t uint64_ta __attribute__ ((aligned (8))) ;
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typedef int64_t int64_ta __attribute__ ((aligned (8))) ;
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typedef TheISA::Addr Addr_a __attribute__ ((aligned (8))) ;
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typedef Addr Addr_a __attribute__ ((aligned (8))) ;
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#else
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#define uint64_ta uint64_t __attribute__ ((aligned (8)))
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#define int64_ta int64_t __attribute__ ((aligned (8)))
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@ -53,9 +53,6 @@ class Linux {};
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///
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class Linux {
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protected:
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typedef TheISA::Addr Addr;
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public:
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//@{
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|
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@ -37,8 +37,6 @@ namespace Linux {
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class ThreadInfo
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{
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protected:
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typedef TheISA::Addr Addr;
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private:
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ExecContext *xc;
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@ -35,35 +35,35 @@
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namespace tru64 {
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struct m_hdr {
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TheISA::Addr mh_next; // 0x00
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TheISA::Addr mh_nextpkt; // 0x08
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TheISA::Addr mh_data; // 0x10
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Addr mh_next; // 0x00
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Addr mh_nextpkt; // 0x08
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Addr mh_data; // 0x10
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int32_t mh_len; // 0x18
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int32_t mh_type; // 0x1C
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int32_t mh_flags; // 0x20
|
||||
int32_t mh_pad0; // 0x24
|
||||
TheISA::Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
|
||||
Addr mh_foo[4]; // 0x28, 0x30, 0x38, 0x40
|
||||
};
|
||||
|
||||
struct pkthdr {
|
||||
int32_t len;
|
||||
int32_t protocolSum;
|
||||
TheISA::Addr rcvif;
|
||||
Addr rcvif;
|
||||
};
|
||||
|
||||
struct m_ext {
|
||||
TheISA::Addr ext_buf; // 0x00
|
||||
TheISA::Addr ext_free; // 0x08
|
||||
Addr ext_buf; // 0x00
|
||||
Addr ext_free; // 0x08
|
||||
uint32_t ext_size; // 0x10
|
||||
uint32_t ext_pad0; // 0x14
|
||||
TheISA::Addr ext_arg; // 0x18
|
||||
Addr ext_arg; // 0x18
|
||||
struct ext_refq {
|
||||
TheISA::Addr forw, back; // 0x20, 0x28
|
||||
Addr forw, back; // 0x20, 0x28
|
||||
} ext_ref;
|
||||
TheISA::Addr uiomove_f; // 0x30
|
||||
Addr uiomove_f; // 0x30
|
||||
int32_t protocolSum; // 0x38
|
||||
int32_t bytesSummed; // 0x3C
|
||||
TheISA::Addr checksum; // 0x40
|
||||
Addr checksum; // 0x40
|
||||
};
|
||||
|
||||
struct mbuf {
|
||||
|
|
|
@ -392,7 +392,7 @@ class Tru64 {
|
|||
/// For stack_create.
|
||||
struct vm_stack {
|
||||
// was void *
|
||||
TheISA::Addr address; //!< address hint
|
||||
Addr address; //!< address hint
|
||||
size_t rsize; //!< red zone size
|
||||
size_t ysize; //!< yellow zone size
|
||||
size_t gsize; //!< green zone size
|
||||
|
@ -401,7 +401,7 @@ class Tru64 {
|
|||
uint64_t align; //!< address alignment
|
||||
uint64_t flags; //!< MAP_FIXED etc.
|
||||
// was struct memalloc_attr *
|
||||
TheISA::Addr attr; //!< allocation policy
|
||||
Addr attr; //!< allocation policy
|
||||
uint64_t reserved; //!< reserved
|
||||
};
|
||||
|
||||
|
@ -433,7 +433,7 @@ class Tru64 {
|
|||
sigset_t sigmask; //!< thread signal mask
|
||||
sigset_t sig; //!< thread pending mask
|
||||
// struct nxm_pth_state *
|
||||
TheISA::Addr pth_id; //!< out-of-line state
|
||||
Addr pth_id; //!< out-of-line state
|
||||
int flags; //!< shared flags
|
||||
#define US_SIGSTACK 0x1 // thread called sigaltstack
|
||||
#define US_ONSTACK 0x2 // thread is running on altstack
|
||||
|
@ -469,12 +469,12 @@ class Tru64 {
|
|||
int nxm_set_quantum; //!< quantum reset value
|
||||
int nxm_sysevent; //!< syscall state
|
||||
// struct nxm_upcall *
|
||||
TheISA::Addr nxm_uc_ret; //!< stack ptr of null thread
|
||||
Addr nxm_uc_ret; //!< stack ptr of null thread
|
||||
// void *
|
||||
TheISA::Addr nxm_tid; //!< scheduler's thread id
|
||||
Addr nxm_tid; //!< scheduler's thread id
|
||||
int64_t nxm_va; //!< page fault address
|
||||
// struct nxm_pth_state *
|
||||
TheISA::Addr nxm_pthid; //!< id of null thread
|
||||
Addr nxm_pthid; //!< id of null thread
|
||||
uint64_t nxm_bound_pcs_count; //!< bound PCS thread count
|
||||
int64_t pad[2]; //!< pad
|
||||
};
|
||||
|
@ -502,9 +502,9 @@ class Tru64 {
|
|||
int nxm_nslots_per_rad; //!< max number of VP slots per RAD
|
||||
int nxm_nrads; //!< max number of RADs
|
||||
// nxm_slot_state_t *
|
||||
TheISA::Addr nxm_slot_state; //!< per-VP slot state
|
||||
Addr nxm_slot_state; //!< per-VP slot state
|
||||
// struct nxm_shared *
|
||||
TheISA::Addr nxm_rad[1]; //!< per-RAD shared areas
|
||||
Addr nxm_rad[1]; //!< per-RAD shared areas
|
||||
};
|
||||
|
||||
/// For nxm_thread_create.
|
||||
|
@ -523,7 +523,7 @@ class Tru64 {
|
|||
int policy; //!< policy
|
||||
int signal_type; //!< signal_type
|
||||
// void *
|
||||
TheISA::Addr pthid; //!< pthid
|
||||
Addr pthid; //!< pthid
|
||||
sigset_t sigmask; //!< sigmask
|
||||
/// Initial register values.
|
||||
struct {
|
||||
|
@ -539,7 +539,7 @@ class Tru64 {
|
|||
/// memory space. Used by stat(), fstat(), and lstat().
|
||||
template <class T>
|
||||
static void
|
||||
copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr, global_stat *host)
|
||||
copyOutStatBuf(FunctionalMemory *mem, Addr addr, global_stat *host)
|
||||
{
|
||||
TypedBufferArg<T> tgt(addr);
|
||||
|
||||
|
@ -565,7 +565,7 @@ class Tru64 {
|
|||
/// memory space. Used by statfs() and fstatfs().
|
||||
template <class T>
|
||||
static void
|
||||
copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr, global_statfs *host)
|
||||
copyOutStatfsBuf(FunctionalMemory *mem, Addr addr, global_statfs *host)
|
||||
{
|
||||
TypedBufferArg<T> tgt(addr);
|
||||
|
||||
|
@ -589,13 +589,13 @@ class Tru64 {
|
|||
|
||||
class F64 {
|
||||
public:
|
||||
static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
|
||||
static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
|
||||
global_stat *host)
|
||||
{
|
||||
Tru64::copyOutStatBuf<Tru64::F64_stat>(mem, addr, host);
|
||||
}
|
||||
|
||||
static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
|
||||
static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
|
||||
global_statfs *host)
|
||||
{
|
||||
Tru64::copyOutStatfsBuf<Tru64::F64_statfs>(mem, addr, host);
|
||||
|
@ -604,13 +604,13 @@ class Tru64 {
|
|||
|
||||
class PreF64 {
|
||||
public:
|
||||
static void copyOutStatBuf(FunctionalMemory *mem, TheISA::Addr addr,
|
||||
static void copyOutStatBuf(FunctionalMemory *mem, Addr addr,
|
||||
global_stat *host)
|
||||
{
|
||||
Tru64::copyOutStatBuf<Tru64::pre_F64_stat>(mem, addr, host);
|
||||
}
|
||||
|
||||
static void copyOutStatfsBuf(FunctionalMemory *mem, TheISA::Addr addr,
|
||||
static void copyOutStatfsBuf(FunctionalMemory *mem, Addr addr,
|
||||
global_statfs *host)
|
||||
{
|
||||
Tru64::copyOutStatfsBuf<Tru64::pre_F64_statfs>(mem, addr, host);
|
||||
|
@ -622,7 +622,7 @@ class Tru64 {
|
|||
/// the simulated memory space. Used by pre_F64_stat(),
|
||||
/// pre_F64_fstat(), and pre_F64_lstat().
|
||||
static void
|
||||
copyOutPreF64StatBuf(FunctionalMemory *mem, TheISA::Addr addr, struct stat *host)
|
||||
copyOutPreF64StatBuf(FunctionalMemory *mem, Addr addr, struct stat *host)
|
||||
{
|
||||
TypedBufferArg<Tru64::pre_F64_stat> tgt(addr);
|
||||
|
||||
|
@ -653,7 +653,6 @@ class Tru64 {
|
|||
getdirentriesFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
#ifdef __CYGWIN__
|
||||
panic("getdirent not implemented on cygwin!");
|
||||
#else
|
||||
|
@ -809,7 +808,6 @@ class Tru64 {
|
|||
nxm_task_initFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
TypedBufferArg<Tru64::nxm_task_attr> attrp(xc->getSyscallArg(0));
|
||||
TypedBufferArg<Addr> configptr_ptr(xc->getSyscallArg(1));
|
||||
|
||||
|
@ -939,7 +937,6 @@ class Tru64 {
|
|||
nxm_thread_createFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
TypedBufferArg<Tru64::nxm_thread_attr> attrp(xc->getSyscallArg(0));
|
||||
TypedBufferArg<uint64_t> kidp(xc->getSyscallArg(1));
|
||||
int thread_index = xc->getSyscallArg(2);
|
||||
|
@ -1079,7 +1076,6 @@ class Tru64 {
|
|||
nxm_blockFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr uaddr = xc->getSyscallArg(0);
|
||||
uint64_t val = xc->getSyscallArg(1);
|
||||
uint64_t secs = xc->getSyscallArg(2);
|
||||
|
@ -1101,7 +1097,6 @@ class Tru64 {
|
|||
nxm_unblockFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr uaddr = xc->getSyscallArg(0);
|
||||
|
||||
cout << xc->cpu->name() << ": nxm_unblock "
|
||||
|
@ -1129,7 +1124,7 @@ class Tru64 {
|
|||
/// Activate exec context waiting on a channel. Just activate one
|
||||
/// by default.
|
||||
static int
|
||||
activate_waiting_context(TheISA::Addr uaddr, Process *process,
|
||||
activate_waiting_context(Addr uaddr, Process *process,
|
||||
bool activate_all = false)
|
||||
{
|
||||
int num_activated = 0;
|
||||
|
@ -1158,7 +1153,7 @@ class Tru64 {
|
|||
|
||||
/// M5 hacked-up lock acquire.
|
||||
static void
|
||||
m5_lock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
|
||||
m5_lock_mutex(Addr uaddr, Process *process, ExecContext *xc)
|
||||
{
|
||||
TypedBufferArg<uint64_t> lockp(uaddr);
|
||||
|
||||
|
@ -1177,7 +1172,7 @@ class Tru64 {
|
|||
|
||||
/// M5 unlock call.
|
||||
static void
|
||||
m5_unlock_mutex(TheISA::Addr uaddr, Process *process, ExecContext *xc)
|
||||
m5_unlock_mutex(Addr uaddr, Process *process, ExecContext *xc)
|
||||
{
|
||||
TypedBufferArg<uint64_t> lockp(uaddr);
|
||||
|
||||
|
@ -1199,7 +1194,6 @@ class Tru64 {
|
|||
m5_mutex_lockFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr uaddr = xc->getSyscallArg(0);
|
||||
|
||||
m5_lock_mutex(uaddr, process, xc);
|
||||
|
@ -1215,7 +1209,6 @@ class Tru64 {
|
|||
m5_mutex_trylockFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr uaddr = xc->getSyscallArg(0);
|
||||
TypedBufferArg<uint64_t> lockp(uaddr);
|
||||
|
||||
|
@ -1236,7 +1229,6 @@ class Tru64 {
|
|||
m5_mutex_unlockFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr uaddr = xc->getSyscallArg(0);
|
||||
|
||||
m5_unlock_mutex(uaddr, process, xc);
|
||||
|
@ -1249,7 +1241,6 @@ class Tru64 {
|
|||
m5_cond_signalFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr cond_addr = xc->getSyscallArg(0);
|
||||
|
||||
// Wake up one process waiting on the condition variable.
|
||||
|
@ -1263,7 +1254,6 @@ class Tru64 {
|
|||
m5_cond_broadcastFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr cond_addr = xc->getSyscallArg(0);
|
||||
|
||||
activate_waiting_context(cond_addr, process, true);
|
||||
|
@ -1276,7 +1266,6 @@ class Tru64 {
|
|||
m5_cond_waitFunc(SyscallDesc *desc, int callnum, Process *process,
|
||||
ExecContext *xc)
|
||||
{
|
||||
using TheISA::Addr;
|
||||
Addr cond_addr = xc->getSyscallArg(0);
|
||||
Addr lock_addr = xc->getSyscallArg(1);
|
||||
TypedBufferArg<uint64_t> condp(cond_addr);
|
||||
|
|
|
@ -54,4 +54,12 @@ typedef int64_t Counter;
|
|||
*/
|
||||
typedef int64_t Tick;
|
||||
|
||||
/**
|
||||
* Address type
|
||||
* This will probably be moved somewhere else in the near future.
|
||||
* This should be at least as big as the biggest address width in use
|
||||
* in the system, which will probably be 64 bits.
|
||||
*/
|
||||
typedef uint64_t Addr;
|
||||
|
||||
#endif // __HOST_H__
|
||||
|
|
|
@ -52,7 +52,6 @@ class SyscallDesc;
|
|||
class Process : public SimObject
|
||||
{
|
||||
protected:
|
||||
typedef TheISA::Addr Addr;
|
||||
typedef TheISA::RegFile RegFile;
|
||||
typedef TheISA::MachInst MachInst;
|
||||
public:
|
||||
|
|
|
@ -52,8 +52,8 @@ namespace AlphaPseudo
|
|||
void dumpstats(ExecContext *xc, Tick delay, Tick period);
|
||||
void dumpresetstats(ExecContext *xc, Tick delay, Tick period);
|
||||
void m5checkpoint(ExecContext *xc, Tick delay, Tick period);
|
||||
uint64_t readfile(ExecContext *xc, TheISA::Addr vaddr, uint64_t len, uint64_t offset);
|
||||
uint64_t readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset);
|
||||
void debugbreak(ExecContext *xc);
|
||||
void switchcpu(ExecContext *xc);
|
||||
void addsymbol(ExecContext *xc, TheISA::Addr addr, TheISA::Addr symbolAddr);
|
||||
void addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr);
|
||||
}
|
||||
|
|
|
@ -90,9 +90,6 @@ class SyscallDesc {
|
|||
|
||||
class BaseBufferArg {
|
||||
|
||||
protected:
|
||||
typedef TheISA::Addr Addr;
|
||||
|
||||
public:
|
||||
|
||||
BaseBufferArg(Addr _addr, int _size) : addr(_addr), size(_size)
|
||||
|
@ -643,7 +640,7 @@ template <class OS>
|
|||
SyscallReturn
|
||||
mmapFunc(SyscallDesc *desc, int num, Process *p, ExecContext *xc)
|
||||
{
|
||||
TheISA::Addr start = xc->getSyscallArg(0);
|
||||
Addr start = xc->getSyscallArg(0);
|
||||
uint64_t length = xc->getSyscallArg(1);
|
||||
// int prot = xc->getSyscallArg(2);
|
||||
int flags = xc->getSyscallArg(3);
|
||||
|
|
|
@ -50,8 +50,6 @@ namespace Kernel { class Binning; }
|
|||
|
||||
class System : public SimObject
|
||||
{
|
||||
protected:
|
||||
typedef TheISA::Addr Addr;
|
||||
public:
|
||||
MemoryController *memctrl;
|
||||
PhysicalMemory *physmem;
|
||||
|
|
|
@ -37,8 +37,6 @@ class ExecContext;
|
|||
template <class T>
|
||||
class VPtr
|
||||
{
|
||||
protected:
|
||||
typedef TheISA::Addr Addr;
|
||||
public:
|
||||
typedef T Type;
|
||||
|
||||
|
|
Loading…
Reference in a new issue