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ARM: Add m5ops and related support for workbegin() and workend() to ARM ISA.

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This commit is contained in:
Gedare Bloom 2011-06-17 12:20:10 -05:00
parent 8b4307f8d8
commit 3f1f16703d
5 changed files with 35 additions and 0 deletions
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1
configs/example/fs.py
View file

@ -137,6 +137,7 @@ elif buildEnv['TARGET_ISA'] == "arm":
test_sys = makeArmSystem(test_mem_mode, test_sys = makeArmSystem(test_mem_mode,
options.machine_type, bm[0], options.machine_type, bm[0],
bare_metal=options.bare_metal) bare_metal=options.bare_metal)
setWorkCountOptions(test_sys, options)
else: else:
fatal("incapable of building non-alpha or non-sparc full system!") fatal("incapable of building non-alpha or non-sparc full system!")

2
src/arch/arm/isa/formats/m5ops.isa
View file

@ -72,6 +72,8 @@ def format M5ops() {{
case 0x53: return new M5addsymbol(machInst); case 0x53: return new M5addsymbol(machInst);
#endif #endif
case 0x54: return new M5panic(machInst); case 0x54: return new M5panic(machInst);
case 0x5a: return new M5workbegin(machInst);
case 0x5b: return new M5workend(machInst);
} }
} }
''' '''

26
src/arch/arm/isa/insts/m5ops.isa
View file

@ -313,4 +313,30 @@ let {{
decoder_output += BasicConstructor.subst(m5panicIop) decoder_output += BasicConstructor.subst(m5panicIop)
exec_output += PredOpExecute.subst(m5panicIop) exec_output += PredOpExecute.subst(m5panicIop)
m5workbeginCode = '''PseudoInst::workbegin(
xc->tcBase(),
join32to64(R1, R0),
join32to64(R3, R2)
);'''
m5workbeginIop = InstObjParams("m5workbegin", "M5workbegin", "PredOp",
{ "code": m5workbeginCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5workbeginIop)
decoder_output += BasicConstructor.subst(m5workbeginIop)
exec_output += PredOpExecute.subst(m5workbeginIop)
m5workendCode = '''PseudoInst::workend(
xc->tcBase(),
join32to64(R1, R0),
join32to64(R3, R2)
);'''
m5workendIop = InstObjParams("m5workend", "M5workend", "PredOp",
{ "code": m5workendCode,
"predicate_test": predicateTest },
["IsNonSpeculative"])
header_output += BasicDeclare.subst(m5workendIop)
decoder_output += BasicConstructor.subst(m5workendIop)
exec_output += PredOpExecute.subst(m5workendIop)
}}; }};

2
util/m5/m5op.h
View file

@ -53,6 +53,8 @@ void m5_debugbreak(void);
void m5_switchcpu(void); void m5_switchcpu(void);
void m5_addsymbol(uint64_t addr, char *symbol); void m5_addsymbol(uint64_t addr, char *symbol);
void m5_panic(void); void m5_panic(void);
void m5_work_begin(uint64_t workid, uint64_t threadid);
void m5_work_end(uint64_t workid, uint64_t threadid);
// These operations are for critical path annotation // These operations are for critical path annotation
void m5a_bsm(char *sm, const void *id, int flags); void m5a_bsm(char *sm, const void *id, int flags);

4
util/m5/m5op_arm.S
View file

@ -84,6 +84,8 @@ func:
#define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func) #define SWITCHCPU INST(m5_op, 0, 0, switchcpu_func)
#define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func) #define ADDSYMBOL(r1,r2) INST(m5_op, r1, r2, addsymbol_func)
#define PANIC INST(m5_op, 0, 0, panic_func) #define PANIC INST(m5_op, 0, 0, panic_func)
#define WORK_BEGIN(r1,r2) INST(m5_op, r1, r2, work_begin_func)
#define WORK_END(r1,r2) INST(m5_op, r1, r2, work_end_func)
#define AN_BSM INST(m5_op, an_bsm, 0, annotate_func) #define AN_BSM INST(m5_op, an_bsm, 0, annotate_func)
#define AN_ESM INST(m5_op, an_esm, 0, annotate_func) #define AN_ESM INST(m5_op, an_esm, 0, annotate_func)
@ -123,6 +125,8 @@ SIMPLE_OP(m5_debugbreak, DEBUGBREAK)
SIMPLE_OP(m5_switchcpu, SWITCHCPU) SIMPLE_OP(m5_switchcpu, SWITCHCPU)
SIMPLE_OP(m5_addsymbol, ADDSYMBOL(0, 1)) SIMPLE_OP(m5_addsymbol, ADDSYMBOL(0, 1))
SIMPLE_OP(m5_panic, PANIC) SIMPLE_OP(m5_panic, PANIC)
SIMPLE_OP(m5_work_begin, WORK_BEGIN(0,1))
SIMPLE_OP(m5_work_end, WORK_END(0,1))
SIMPLE_OP(m5a_bsm, AN_BSM) SIMPLE_OP(m5a_bsm, AN_BSM)
SIMPLE_OP(m5a_esm, AN_ESM) SIMPLE_OP(m5a_esm, AN_ESM)