arm, config: Add missing IOCache in bL config
This patch adds an IOCache to the example bigLITTLE configuration. An IOCache is required for correct DMA transfers when we have caches in the system. Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
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c642d6fc37
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2 changed files with 26 additions and 12 deletions
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@ -174,7 +174,7 @@ class AtomicCluster(CpuCluster):
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class SimpleSystem(LinuxArmSystem):
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cache_line_size = 64
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def __init__(self, **kwargs):
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def __init__(self, caches, mem_size, **kwargs):
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super(SimpleSystem, self).__init__(**kwargs)
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self.voltage_domain = VoltageDomain(voltage="1.0V")
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@ -196,8 +196,16 @@ class SimpleSystem(LinuxArmSystem):
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# CPUs->PIO
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self.iobridge = Bridge(delay='50ns')
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# Device DMA -> MEM
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self.dmabridge = Bridge(delay='50ns',
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ranges=self.realview._mem_regions)
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mem_range = self.realview._mem_regions[0]
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mem_range_size = long(mem_range[1]) - long(mem_range[0])
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assert mem_range_size >= long(Addr(mem_size))
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self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
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self._caches = caches
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if self._caches:
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self.iocache = IOCache(addr_ranges=[self._mem_range])
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else:
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self.dmabridge = Bridge(delay='50ns',
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ranges=[self._mem_range])
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self._pci_devices = 0
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self._clusters = []
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@ -212,8 +220,12 @@ class SimpleSystem(LinuxArmSystem):
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self.iobridge.master = self.iobus.slave
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self.iobridge.slave = self.membus.master
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self.dmabridge.master = self.membus.slave
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self.dmabridge.slave = self.iobus.master
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if self._caches:
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self.iocache.mem_side = self.membus.slave
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self.iocache.cpu_side = self.iobus.master
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else:
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self.dmabridge.master = self.membus.slave
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self.dmabridge.slave = self.iobus.master
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self.gic_cpu_addr = self.realview.gic.cpu_addr
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self.realview.attachOnChipIO(self.membus, self.iobridge)
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@ -79,14 +79,13 @@ class LittleCluster(devices.CpuCluster):
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cpu_voltage, *cpu_config)
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def createSystem(kernel, bootscript, disks=[]):
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sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
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def createSystem(caches, kernel, bootscript, disks=[]):
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sys = devices.SimpleSystem(caches, default_mem_size,
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kernel=SysPaths.binary(kernel),
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readfile=bootscript,
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machine_type="DTOnly")
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mem_region = sys.realview._mem_regions[0]
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sys.mem_ctrls = SimpleMemory(
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range=AddrRange(start=mem_region[0], size=default_mem_size))
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sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
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sys.mem_ctrls.port = sys.membus.master
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sys.connect()
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@ -159,8 +158,11 @@ def main():
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root = Root(full_system=True)
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disks = default_disk if len(options.disk) == 0 else options.disk
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system = createSystem(options.kernel, options.bootscript, disks=disks)
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disks = [default_disk] if len(options.disk) == 0 else options.disk
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system = createSystem(options.caches,
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options.kernel,
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options.bootscript,
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disks=disks)
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root.system = system
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system.boot_osflags = " ".join(kernel_cmd)
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