arm, config: Add missing IOCache in bL config

This patch adds an IOCache to the example bigLITTLE
configuration. An IOCache is required for correct DMA
transfers when we have caches in the system.

Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabor Dozsa 2016-12-06 17:10:36 +00:00
parent c642d6fc37
commit 3ef797623a
2 changed files with 26 additions and 12 deletions

View file

@ -174,7 +174,7 @@ class AtomicCluster(CpuCluster):
class SimpleSystem(LinuxArmSystem):
cache_line_size = 64
def __init__(self, **kwargs):
def __init__(self, caches, mem_size, **kwargs):
super(SimpleSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V")
@ -196,8 +196,16 @@ class SimpleSystem(LinuxArmSystem):
# CPUs->PIO
self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
mem_range_size = long(mem_range[1]) - long(mem_range[0])
assert mem_range_size >= long(Addr(mem_size))
self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self._mem_range])
else:
self.dmabridge = Bridge(delay='50ns',
ranges=self.realview._mem_regions)
ranges=[self._mem_range])
self._pci_devices = 0
self._clusters = []
@ -212,6 +220,10 @@ class SimpleSystem(LinuxArmSystem):
self.iobridge.master = self.iobus.slave
self.iobridge.slave = self.membus.master
if self._caches:
self.iocache.mem_side = self.membus.slave
self.iocache.cpu_side = self.iobus.master
else:
self.dmabridge.master = self.membus.slave
self.dmabridge.slave = self.iobus.master

View file

@ -79,14 +79,13 @@ class LittleCluster(devices.CpuCluster):
cpu_voltage, *cpu_config)
def createSystem(kernel, bootscript, disks=[]):
sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel),
def createSystem(caches, kernel, bootscript, disks=[]):
sys = devices.SimpleSystem(caches, default_mem_size,
kernel=SysPaths.binary(kernel),
readfile=bootscript,
machine_type="DTOnly")
mem_region = sys.realview._mem_regions[0]
sys.mem_ctrls = SimpleMemory(
range=AddrRange(start=mem_region[0], size=default_mem_size))
sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
sys.mem_ctrls.port = sys.membus.master
sys.connect()
@ -159,8 +158,11 @@ def main():
root = Root(full_system=True)
disks = default_disk if len(options.disk) == 0 else options.disk
system = createSystem(options.kernel, options.bootscript, disks=disks)
disks = [default_disk] if len(options.disk) == 0 else options.disk
system = createSystem(options.caches,
options.kernel,
options.bootscript,
disks=disks)
root.system = system
system.boot_osflags = " ".join(kernel_cmd)