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arm, config: Add missing IOCache in bL config

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This patch adds an IOCache to the example bigLITTLE
configuration. An IOCache is required for correct DMA
transfers when we have caches in the system.

Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
This commit is contained in:
Gabor Dozsa 2016-12-06 17:10:36 +00:00
parent c642d6fc37
commit 3ef797623a
2 changed files with 26 additions and 12 deletions
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16
configs/example/arm/devices.py
View file

@ -174,7 +174,7 @@ class AtomicCluster(CpuCluster):
class SimpleSystem(LinuxArmSystem): class SimpleSystem(LinuxArmSystem):
cache_line_size = 64 cache_line_size = 64
def __init__(self, **kwargs): def __init__(self, caches, mem_size, **kwargs):
super(SimpleSystem, self).__init__(**kwargs) super(SimpleSystem, self).__init__(**kwargs)
self.voltage_domain = VoltageDomain(voltage="1.0V") self.voltage_domain = VoltageDomain(voltage="1.0V")
@ -196,8 +196,16 @@ class SimpleSystem(LinuxArmSystem):
# CPUs->PIO # CPUs->PIO
self.iobridge = Bridge(delay='50ns') self.iobridge = Bridge(delay='50ns')
# Device DMA -> MEM # Device DMA -> MEM
mem_range = self.realview._mem_regions[0]
mem_range_size = long(mem_range[1]) - long(mem_range[0])
assert mem_range_size >= long(Addr(mem_size))
self._mem_range = AddrRange(start=mem_range[0], size=mem_size)
self._caches = caches
if self._caches:
self.iocache = IOCache(addr_ranges=[self._mem_range])
else:
self.dmabridge = Bridge(delay='50ns', self.dmabridge = Bridge(delay='50ns',
ranges=self.realview._mem_regions) ranges=[self._mem_range])
self._pci_devices = 0 self._pci_devices = 0
self._clusters = [] self._clusters = []
@ -212,6 +220,10 @@ class SimpleSystem(LinuxArmSystem):
self.iobridge.master = self.iobus.slave self.iobridge.master = self.iobus.slave
self.iobridge.slave = self.membus.master self.iobridge.slave = self.membus.master
if self._caches:
self.iocache.mem_side = self.membus.slave
self.iocache.cpu_side = self.iobus.master
else:
self.dmabridge.master = self.membus.slave self.dmabridge.master = self.membus.slave
self.dmabridge.slave = self.iobus.master self.dmabridge.slave = self.iobus.master

16
configs/example/arm/fs_bigLITTLE.py
View file

@ -79,14 +79,13 @@ class LittleCluster(devices.CpuCluster):
cpu_voltage, *cpu_config) cpu_voltage, *cpu_config)
def createSystem(kernel, bootscript, disks=[]): def createSystem(caches, kernel, bootscript, disks=[]):
sys = devices.SimpleSystem(kernel=SysPaths.binary(kernel), sys = devices.SimpleSystem(caches, default_mem_size,
kernel=SysPaths.binary(kernel),
readfile=bootscript, readfile=bootscript,
machine_type="DTOnly") machine_type="DTOnly")
mem_region = sys.realview._mem_regions[0] sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
sys.mem_ctrls = SimpleMemory(
range=AddrRange(start=mem_region[0], size=default_mem_size))
sys.mem_ctrls.port = sys.membus.master sys.mem_ctrls.port = sys.membus.master
sys.connect() sys.connect()
@ -159,8 +158,11 @@ def main():
root = Root(full_system=True) root = Root(full_system=True)
disks = default_disk if len(options.disk) == 0 else options.disk disks = [default_disk] if len(options.disk) == 0 else options.disk
system = createSystem(options.kernel, options.bootscript, disks=disks) system = createSystem(options.caches,
options.kernel,
options.bootscript,
disks=disks)
root.system = system root.system = system
system.boot_osflags = " ".join(kernel_cmd) system.boot_osflags = " ".join(kernel_cmd)