Work towards factoring isa_traits.hh into smaller, more specialized files.
arch/SConscript: Sorted the switch headers, and added registerfile.hh, constants.hh, types.hh, and utility.hh. arch/alpha/isa_traits.hh: Moved the register file types to registerfile.hh, small functions to utility.hh, and cleaned out alot of stuff that isn't necessary anymore. base/loader/ecoff_object.cc: base/loader/elf_object.cc: cpu/pc_event.hh: cpu/static_inst.hh: mem/port.hh: sim/faults.cc: sim/system.hh: base/misc.hh isn't included through isa_traits.hh anymore. cpu/simple/cpu.cc: Added include for arch/utility.hh --HG-- extra : convert_revision : 24f65f330f87e3c909c939596cfcf48336022eaf
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10 changed files with 20 additions and 155 deletions
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@ -45,13 +45,17 @@ sources = []
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# List of headers to generate
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isa_switch_hdrs = Split('''
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isa_traits.hh
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tlb.hh
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process.hh
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arguments.hh
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stacktrace.hh
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vtophys.hh
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constants.hh
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faults.hh
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isa_traits.hh
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process.hh
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registerfile.hh
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stacktrace.hh
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tlb.hh
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types.hh
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utility.hh
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vtophys.hh
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''')
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# Generate the header. target[0] is the full path of the output
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@ -34,17 +34,10 @@ using namespace LittleEndianGuest;
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#include "arch/alpha/types.hh"
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#include "arch/alpha/constants.hh"
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#include "base/misc.hh"
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#include "arch/alpha/registerfile.hh"
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#include "config/full_system.hh"
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#include "sim/host.hh"
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#include "sim/faults.hh"
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class ExecContext;
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class FastCPU;
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class FullCPU;
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class Checkpoint;
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class StaticInst;
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class StaticInstPtr;
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#if !FULL_SYSTEM
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@ -86,13 +79,6 @@ class SyscallReturn {
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namespace AlphaISA
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{
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typedef IntReg IntRegFile[NumIntRegs];
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typedef union {
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uint64_t q[NumFloatRegs]; // integer qword view
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double d[NumFloatRegs]; // double-precision floating point view
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} FloatRegFile;
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// redirected register map, really only used for the full system case.
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extern const int reg_redir[NumIntRegs];
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@ -101,130 +87,9 @@ extern const int reg_redir[NumIntRegs];
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#include "arch/alpha/isa_fullsys_traits.hh"
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#endif
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class MiscRegFile {
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protected:
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uint64_t fpcr; // floating point condition codes
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uint64_t uniq; // process-unique register
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bool lock_flag; // lock flag for LL/SC
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Addr lock_addr; // lock address for LL/SC
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public:
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MiscReg readReg(int misc_reg);
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//These functions should be removed once the simplescalar cpu model
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//has been replaced.
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int getInstAsid();
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int getDataAsid();
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MiscReg readRegWithEffect(int misc_reg, Fault &fault, ExecContext *xc);
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Fault setReg(int misc_reg, const MiscReg &val);
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Fault setRegWithEffect(int misc_reg, const MiscReg &val,
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ExecContext *xc);
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void copyMiscRegs(ExecContext *xc);
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#if FULL_SYSTEM
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protected:
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typedef uint64_t InternalProcReg;
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InternalProcReg ipr[NumInternalProcRegs]; // Internal processor regs
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private:
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InternalProcReg readIpr(int idx, Fault &fault, ExecContext *xc);
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Fault setIpr(int idx, InternalProcReg val, ExecContext *xc);
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void copyIprs(ExecContext *xc);
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#endif
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friend class RegFile;
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};
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struct RegFile {
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegs; // control register file
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Addr pc; // program counter
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Addr npc; // next-cycle program counter
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Addr nnpc;
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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inline int instAsid()
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{ return miscRegs.getInstAsid(); }
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inline int dataAsid()
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{ return miscRegs.getDataAsid(); }
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#endif // FULL_SYSTEM
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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};
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static inline ExtMachInst makeExtMI(MachInst inst, const uint64_t &pc);
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StaticInstPtr decodeInst(ExtMachInst);
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static inline bool isCallerSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 1 && reg <= 8 || reg >= 22 && reg <= 25 || reg == 27);
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}
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static inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
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panic("register classification not implemented");
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return (reg >= 9 && reg <= 15);
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}
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static inline bool isCallerSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline bool isCalleeSaveFloatRegister(unsigned int reg) {
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panic("register classification not implemented");
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return false;
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}
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static inline Addr alignAddress(const Addr &addr,
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unsigned int nbytes) {
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return (addr & ~(nbytes - 1));
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}
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// Instruction address compression hooks
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static inline Addr realPCToFetchPC(const Addr &addr) {
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return addr;
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}
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static inline Addr fetchPCToRealPC(const Addr &addr) {
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return addr;
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}
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// the size of "fetched" instructions (not necessarily the size
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// of real instructions for PISA)
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static inline size_t fetchInstSize() {
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return sizeof(MachInst);
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}
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static inline MachInst makeRegisterCopy(int dest, int src) {
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panic("makeRegisterCopy not implemented");
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return 0;
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}
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// Machine operations
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void saveMachineReg(AnyReg &savereg, const RegFile ®_file,
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int regnum);
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void restoreMachineReg(RegFile ®s, const AnyReg ®,
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int regnum);
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/**
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* Function to insure ISA semantics about 0 registers.
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* @param xc The execution context.
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*/
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template <class XC>
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void zeroRegisters(XC *xc);
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#if !FULL_SYSTEM
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static inline void setSyscallReturn(SyscallReturn return_value, RegFile *regs)
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{
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#endif
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};
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static inline AlphaISA::ExtMachInst
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AlphaISA::makeExtMI(AlphaISA::MachInst inst, const uint64_t &pc) {
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#if FULL_SYSTEM
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AlphaISA::ExtMachInst ext_inst = inst;
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if (pc && 0x1)
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return ext_inst|=(static_cast<AlphaISA::ExtMachInst>(pc & 0x1) << 32);
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else
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return ext_inst;
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#else
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return AlphaISA::ExtMachInst(inst);
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#endif
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}
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#endif // __ARCH_ALPHA_ISA_TRAITS_HH__
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@ -29,6 +29,7 @@
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#include <string>
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#include "base/loader/ecoff_object.hh"
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#include "base/misc.hh"
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#include "base/loader/symtab.hh"
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#include "base/trace.hh" // for DPRINTF
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@ -42,6 +42,7 @@
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#include "libelf/gelf.h"
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#include "base/loader/elf_object.hh"
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#include "base/misc.hh"
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#include "base/loader/symtab.hh"
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@ -31,6 +31,8 @@
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#include <vector>
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#include "base/misc.hh"
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class ExecContext;
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class PCEventQueue;
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@ -35,6 +35,7 @@
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#include <sstream>
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#include <string>
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#include "arch/utility.hh"
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#include "base/cprintf.hh"
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#include "base/inifile.hh"
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#include "base/loader/symtab.hh"
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@ -33,6 +33,7 @@
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#include <string>
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#include "base/hashmap.hh"
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#include "base/misc.hh"
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#include "base/refcnt.hh"
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#include "cpu/op_class.hh"
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#include "sim/host.hh"
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@ -42,6 +42,7 @@
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#include <list>
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#include <inttypes.h>
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#include "base/misc.hh"
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#include "base/range.hh"
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#include "mem/packet.hh"
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#include "mem/request.hh"
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@ -26,6 +26,7 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "base/misc.hh"
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#include "sim/faults.hh"
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#include "cpu/exec_context.hh"
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#include "cpu/base.hh"
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@ -32,8 +32,9 @@
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#include <string>
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#include <vector>
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#include "base/statistics.hh"
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#include "base/loader/symtab.hh"
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#include "base/misc.hh"
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#include "base/statistics.hh"
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#include "cpu/pc_event.hh"
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#include "sim/sim_object.hh"
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#if FULL_SYSTEM
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