Memory: Rename LOCKED for load locked store conditional to LLSC.
This commit is contained in:
parent
ca85981478
commit
3e5f487663
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@ -45,8 +45,8 @@ decode OPCODE default Unknown::unknown() {
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0x0c: ldwu({{ Ra.uq = Mem.uw; }});
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0x0c: ldwu({{ Ra.uq = Mem.uw; }});
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0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
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0x0b: ldq_u({{ Ra = Mem.uq; }}, ea_code = {{ EA = (Rb + disp) & ~7; }});
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0x23: ldt({{ Fa = Mem.df; }});
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0x23: ldt({{ Fa = Mem.df; }});
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0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LOCKED);
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0x2a: ldl_l({{ Ra.sl = Mem.sl; }}, mem_flags = LLSC);
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0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LOCKED);
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0x2b: ldq_l({{ Ra.uq = Mem.uq; }}, mem_flags = LLSC);
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#ifdef USE_COPY
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#ifdef USE_COPY
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0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
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0x20: MiscPrefetch::copy_load({{ EA = Ra; }},
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{{ fault = xc->copySrcTranslate(EA); }},
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{{ fault = xc->copySrcTranslate(EA); }},
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@ -87,7 +87,7 @@ decode OPCODE default Unknown::unknown() {
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if (tmp == 1) {
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if (tmp == 1) {
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xc->setStCondFailures(0);
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xc->setStCondFailures(0);
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}
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}
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}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
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}}, mem_flags = LLSC, inst_flags = IsStoreConditional);
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0x2f: stq_c({{ Mem.uq = Ra; }},
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0x2f: stq_c({{ Mem.uq = Ra; }},
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{{
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{{
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uint64_t tmp = write_result;
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uint64_t tmp = write_result;
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@ -105,7 +105,7 @@ decode OPCODE default Unknown::unknown() {
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// only.
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// only.
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xc->setStCondFailures(0);
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xc->setStCondFailures(0);
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}
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}
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}}, mem_flags = LOCKED, inst_flags = IsStoreConditional);
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}}, mem_flags = LLSC, inst_flags = IsStoreConditional);
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}
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}
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format IntegerOperate {
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format IntegerOperate {
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@ -178,7 +178,7 @@ output decoder {{
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if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
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if (HW_LDST_PHYS) memAccessFlags.set(Request::PHYSICAL);
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if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
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if (HW_LDST_ALT) memAccessFlags.set(Request::ALTMODE);
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if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
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if (HW_LDST_VPTE) memAccessFlags.set(Request::VPTE);
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if (HW_LDST_LOCK) memAccessFlags.set(Request::LOCKED);
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if (HW_LDST_LOCK) memAccessFlags.set(Request::LLSC);
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}
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}
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std::string
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std::string
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@ -2089,7 +2089,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x6: decode OPCODE_LO {
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0x6: decode OPCODE_LO {
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format LoadMemory {
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format LoadMemory {
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0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LOCKED);
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0x0: ll({{ Rt.uw = Mem.uw; }}, mem_flags=LLSC);
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0x1: lwc1({{ Ft.uw = Mem.uw; }});
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0x1: lwc1({{ Ft.uw = Mem.uw; }});
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0x5: ldc1({{ Ft.ud = Mem.ud; }});
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0x5: ldc1({{ Ft.ud = Mem.ud; }});
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}
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}
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@ -2103,7 +2103,7 @@ decode OPCODE_HI default Unknown::unknown() {
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0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
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0x0: StoreCond::sc({{ Mem.uw = Rt.uw;}},
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{{ uint64_t tmp = write_result;
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{{ uint64_t tmp = write_result;
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Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
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Rt.uw = (tmp == 0 || tmp == 1) ? tmp : Rt.uw;
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}}, mem_flags=LOCKED, inst_flags = IsStoreConditional);
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}}, mem_flags=LLSC, inst_flags = IsStoreConditional);
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format StoreMemory {
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format StoreMemory {
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0x1: swc1({{ Mem.uw = Ft.uw;}});
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0x1: swc1({{ Mem.uw = Ft.uw;}});
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@ -240,8 +240,8 @@ CheckerCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// verify this data.
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// verify this data.
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if (unverifiedReq &&
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if (unverifiedReq &&
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!(unverifiedReq->isUncacheable()) &&
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!(unverifiedReq->isUncacheable()) &&
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(!(unverifiedReq->isLocked()) ||
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(!(unverifiedReq->isLlsc()) ||
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((unverifiedReq->isLocked()) &&
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((unverifiedReq->isLlsc()) &&
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unverifiedReq->getExtraData() == 1))) {
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unverifiedReq->getExtraData() == 1))) {
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T inst_data;
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T inst_data;
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/*
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/*
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@ -355,7 +355,7 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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Request *memReq = cache_req->dataPkt->req;
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Request *memReq = cache_req->dataPkt->req;
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if (cache_req->dataPkt->isWrite() && memReq->isLocked()) {
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if (cache_req->dataPkt->isWrite() && memReq->isLlsc()) {
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assert(cache_req->inst->isStoreConditional());
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assert(cache_req->inst->isStoreConditional());
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DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
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DPRINTF(InOrderCachePort, "Evaluating Store Conditional access\n");
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do_access = TheISA::handleLockedWrite(cpu, memReq);
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do_access = TheISA::handleLockedWrite(cpu, memReq);
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@ -395,7 +395,7 @@ CacheUnit::doDataAccess(DynInstPtr inst)
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cacheStatus = cacheWaitResponse;
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cacheStatus = cacheWaitResponse;
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cacheBlocked = false;
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cacheBlocked = false;
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}
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}
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} else if (!do_access && memReq->isLocked()){
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} else if (!do_access && memReq->isLlsc()){
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// Store-Conditional instructions complete even if they "failed"
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// Store-Conditional instructions complete even if they "failed"
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assert(cache_req->inst->isStoreConditional());
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assert(cache_req->inst->isStoreConditional());
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cache_req->setCompleted(true);
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cache_req->setCompleted(true);
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@ -471,7 +471,7 @@ CacheUnit::processCacheCompletion(PacketPtr pkt)
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if (inst->isLoad()) {
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if (inst->isLoad()) {
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assert(cache_pkt->isRead());
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assert(cache_pkt->isRead());
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if (cache_pkt->req->isLocked()) {
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if (cache_pkt->req->isLlsc()) {
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DPRINTF(InOrderCachePort,
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DPRINTF(InOrderCachePort,
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"[tid:%u]: Handling Load-Linked for [sn:%u]\n",
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"[tid:%u]: Handling Load-Linked for [sn:%u]\n",
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tid, inst->seqNum);
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tid, inst->seqNum);
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@ -514,7 +514,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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"storeHead: %i addr: %#x\n",
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"storeHead: %i addr: %#x\n",
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load_idx, store_idx, storeHead, req->getPaddr());
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load_idx, store_idx, storeHead, req->getPaddr());
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if (req->isLocked()) {
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if (req->isLlsc()) {
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// Disable recording the result temporarily. Writing to misc
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// Disable recording the result temporarily. Writing to misc
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// regs normally updates the result, but this is not the
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// regs normally updates the result, but this is not the
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// desired behavior when handling store conditionals.
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// desired behavior when handling store conditionals.
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@ -647,7 +647,7 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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if (!lsq->cacheBlocked()) {
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if (!lsq->cacheBlocked()) {
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PacketPtr data_pkt =
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PacketPtr data_pkt =
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new Packet(req,
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new Packet(req,
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(req->isLocked() ?
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(req->isLlsc() ?
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MemCmd::LoadLockedReq : MemCmd::ReadReq),
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MemCmd::LoadLockedReq : MemCmd::ReadReq),
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Packet::Broadcast);
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Packet::Broadcast);
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data_pkt->dataStatic(load_inst->memData);
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data_pkt->dataStatic(load_inst->memData);
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@ -652,7 +652,7 @@ LSQUnit<Impl>::writebackStores()
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MemCmd command =
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MemCmd command =
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req->isSwap() ? MemCmd::SwapReq :
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req->isSwap() ? MemCmd::SwapReq :
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(req->isLocked() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
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(req->isLlsc() ? MemCmd::StoreCondReq : MemCmd::WriteReq);
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PacketPtr data_pkt = new Packet(req, command,
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PacketPtr data_pkt = new Packet(req, command,
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Packet::Broadcast);
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Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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data_pkt->dataStatic(inst->memData);
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@ -1256,7 +1256,7 @@ BackEnd<Impl>::executeInsts()
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// ++iewExecStoreInsts;
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// ++iewExecStoreInsts;
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if (!(inst->req->isLocked())) {
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if (!(inst->req->isLlsc())) {
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inst->setExecuted();
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inst->setExecuted();
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instToCommit(inst);
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instToCommit(inst);
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@ -381,7 +381,7 @@ InorderBackEnd<Impl>::write(MemReqPtr &req, T &data, int store_idx)
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}
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}
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}
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}
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/*
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/*
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if (req->isLocked()) {
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if (req->isLlsc()) {
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if (req->isUncacheable()) {
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if (req->isUncacheable()) {
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// Don't update result register (see stq_c in isa_desc)
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// Don't update result register (see stq_c in isa_desc)
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req->result = 2;
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req->result = 2;
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@ -577,7 +577,7 @@ OzoneLSQ<Impl>::writebackStores()
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MemAccessResult result = dcacheInterface->access(req);
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MemAccessResult result = dcacheInterface->access(req);
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//@todo temp fix for LL/SC (works fine for 1 CPU)
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//@todo temp fix for LL/SC (works fine for 1 CPU)
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if (req->isLocked()) {
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if (req->isLlsc()) {
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req->result=1;
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req->result=1;
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panic("LL/SC! oh no no support!!!");
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panic("LL/SC! oh no no support!!!");
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}
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}
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@ -596,7 +596,7 @@ OzoneLSQ<Impl>::writebackStores()
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Event *wb = NULL;
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Event *wb = NULL;
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/*
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/*
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typename IEW::LdWritebackEvent *wb = NULL;
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typename IEW::LdWritebackEvent *wb = NULL;
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if (req->isLocked()) {
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if (req->isLlsc()) {
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// Stx_C does not generate a system port transaction.
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// Stx_C does not generate a system port transaction.
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req->result=0;
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req->result=0;
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wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
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wb = new typename IEW::LdWritebackEvent(storeQueue[storeWBIdx].inst,
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@ -630,7 +630,7 @@ OzoneLSQ<Impl>::writebackStores()
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// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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// storeQueue[storeWBIdx].inst->seqNum);
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// storeQueue[storeWBIdx].inst->seqNum);
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if (req->isLocked()) {
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if (req->isLlsc()) {
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// Stx_C does not generate a system port transaction.
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// Stx_C does not generate a system port transaction.
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req->result=1;
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req->result=1;
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typename BackEnd::LdWritebackEvent *wb =
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typename BackEnd::LdWritebackEvent *wb =
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@ -635,7 +635,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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PacketPtr data_pkt =
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PacketPtr data_pkt =
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new Packet(req,
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new Packet(req,
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(req->isLocked() ?
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(req->isLlsc() ?
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MemCmd::LoadLockedReq : Packet::ReadReq),
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MemCmd::LoadLockedReq : Packet::ReadReq),
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Packet::Broadcast);
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Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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data_pkt->dataStatic(inst->memData);
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@ -662,7 +662,7 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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return NoFault;
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return NoFault;
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}
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}
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if (req->isLocked()) {
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if (req->isLlsc()) {
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cpu->lockFlag = true;
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cpu->lockFlag = true;
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}
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}
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@ -589,7 +589,7 @@ OzoneLWLSQ<Impl>::writebackStores()
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MemCmd command =
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MemCmd command =
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req->isSwap() ? MemCmd::SwapReq :
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req->isSwap() ? MemCmd::SwapReq :
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(req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
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(req->isLlsc() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
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PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
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PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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data_pkt->dataStatic(inst->memData);
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@ -606,7 +606,7 @@ OzoneLWLSQ<Impl>::writebackStores()
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inst->seqNum);
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inst->seqNum);
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// @todo: Remove this SC hack once the memory system handles it.
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// @todo: Remove this SC hack once the memory system handles it.
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if (req->isLocked()) {
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if (req->isLlsc()) {
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if (req->isUncacheable()) {
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if (req->isUncacheable()) {
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req->setExtraData(2);
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req->setExtraData(2);
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} else {
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} else {
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@ -664,7 +664,7 @@ OzoneLWLSQ<Impl>::writebackStores()
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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if (result != MA_HIT && dcacheInterface->doEvents()) {
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store_event->miss = true;
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store_event->miss = true;
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typename BackEnd::LdWritebackEvent *wb = NULL;
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typename BackEnd::LdWritebackEvent *wb = NULL;
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if (req->isLocked()) {
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if (req->isLlsc()) {
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wb = new typename BackEnd::LdWritebackEvent(inst,
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wb = new typename BackEnd::LdWritebackEvent(inst,
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be);
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be);
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store_event->wbEvent = wb;
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store_event->wbEvent = wb;
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@ -691,7 +691,7 @@ OzoneLWLSQ<Impl>::writebackStores()
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// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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// DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
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// inst->seqNum);
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// inst->seqNum);
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if (req->isLocked()) {
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if (req->isLlsc()) {
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// Stx_C does not generate a system port
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// Stx_C does not generate a system port
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// transaction in the 21264, but that might be
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// transaction in the 21264, but that might be
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// hard to accomplish in this model.
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// hard to accomplish in this model.
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@ -322,7 +322,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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// Now do the access.
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// Now do the access.
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if (fault == NoFault) {
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if (fault == NoFault) {
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Packet pkt = Packet(req,
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Packet pkt = Packet(req,
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req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
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req->isLlsc() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
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Packet::Broadcast);
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Packet::Broadcast);
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pkt.dataStatic(dataPtr);
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pkt.dataStatic(dataPtr);
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@ -338,7 +338,7 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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assert(!pkt.isError());
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assert(!pkt.isError());
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if (req->isLocked()) {
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if (req->isLlsc()) {
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TheISA::handleLockedRead(thread, req);
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TheISA::handleLockedRead(thread, req);
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}
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}
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}
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}
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@ -462,7 +462,7 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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MemCmd cmd = MemCmd::WriteReq; // default
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MemCmd cmd = MemCmd::WriteReq; // default
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bool do_access = true; // flag to suppress cache access
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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if (req->isLlsc()) {
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cmd = MemCmd::StoreCondReq;
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cmd = MemCmd::StoreCondReq;
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do_access = TheISA::handleLockedWrite(thread, req);
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do_access = TheISA::handleLockedWrite(thread, req);
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} else if (req->isSwap()) {
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} else if (req->isSwap()) {
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@ -290,7 +290,7 @@ TimingSimpleCPU::sendData(Fault fault, RequestPtr req,
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} else {
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} else {
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bool do_access = true; // flag to suppress cache access
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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if (req->isLlsc()) {
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do_access = TheISA::handleLockedWrite(thread, req);
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do_access = TheISA::handleLockedWrite(thread, req);
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} else if (req->isCondSwap()) {
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} else if (req->isCondSwap()) {
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assert(res);
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assert(res);
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@ -384,11 +384,11 @@ TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
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MemCmd cmd;
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MemCmd cmd;
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if (read) {
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if (read) {
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cmd = MemCmd::ReadReq;
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cmd = MemCmd::ReadReq;
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if (req->isLocked())
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if (req->isLlsc())
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cmd = MemCmd::LoadLockedReq;
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cmd = MemCmd::LoadLockedReq;
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} else {
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} else {
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cmd = MemCmd::WriteReq;
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cmd = MemCmd::WriteReq;
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if (req->isLocked()) {
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if (req->isLlsc()) {
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cmd = MemCmd::StoreCondReq;
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cmd = MemCmd::StoreCondReq;
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} else if (req->isSwap()) {
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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cmd = MemCmd::SwapReq;
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||||||
|
@ -452,7 +452,7 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
|
||||||
_status = DTBWaitResponse;
|
_status = DTBWaitResponse;
|
||||||
if (split_addr > addr) {
|
if (split_addr > addr) {
|
||||||
RequestPtr req1, req2;
|
RequestPtr req1, req2;
|
||||||
assert(!req->isLocked() && !req->isSwap());
|
assert(!req->isLlsc() && !req->isSwap());
|
||||||
req->splitOnVaddr(split_addr, req1, req2);
|
req->splitOnVaddr(split_addr, req1, req2);
|
||||||
|
|
||||||
typedef SplitDataTranslation::WholeTranslationState WholeState;
|
typedef SplitDataTranslation::WholeTranslationState WholeState;
|
||||||
|
@ -571,7 +571,7 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
|
||||||
_status = DTBWaitResponse;
|
_status = DTBWaitResponse;
|
||||||
if (split_addr > addr) {
|
if (split_addr > addr) {
|
||||||
RequestPtr req1, req2;
|
RequestPtr req1, req2;
|
||||||
assert(!req->isLocked() && !req->isSwap());
|
assert(!req->isLlsc() && !req->isSwap());
|
||||||
req->splitOnVaddr(split_addr, req1, req2);
|
req->splitOnVaddr(split_addr, req1, req2);
|
||||||
|
|
||||||
typedef SplitDataTranslation::WholeTranslationState WholeState;
|
typedef SplitDataTranslation::WholeTranslationState WholeState;
|
||||||
|
@ -904,7 +904,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
|
||||||
|
|
||||||
// the locked flag may be cleared on the response packet, so check
|
// the locked flag may be cleared on the response packet, so check
|
||||||
// pkt->req and not pkt to see if it was a load-locked
|
// pkt->req and not pkt to see if it was a load-locked
|
||||||
if (pkt->isRead() && pkt->req->isLocked()) {
|
if (pkt->isRead() && pkt->req->isLlsc()) {
|
||||||
TheISA::handleLockedRead(thread, pkt->req);
|
TheISA::handleLockedRead(thread, pkt->req);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
4
src/mem/cache/blk.hh
vendored
4
src/mem/cache/blk.hh
vendored
|
@ -218,7 +218,7 @@ class CacheBlk
|
||||||
*/
|
*/
|
||||||
void trackLoadLocked(PacketPtr pkt)
|
void trackLoadLocked(PacketPtr pkt)
|
||||||
{
|
{
|
||||||
assert(pkt->isLocked());
|
assert(pkt->isLlsc());
|
||||||
lockList.push_front(Lock(pkt->req));
|
lockList.push_front(Lock(pkt->req));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -236,7 +236,7 @@ class CacheBlk
|
||||||
bool checkWrite(PacketPtr pkt)
|
bool checkWrite(PacketPtr pkt)
|
||||||
{
|
{
|
||||||
Request *req = pkt->req;
|
Request *req = pkt->req;
|
||||||
if (pkt->isLocked()) {
|
if (pkt->isLlsc()) {
|
||||||
// it's a store conditional... have to check for matching
|
// it's a store conditional... have to check for matching
|
||||||
// load locked.
|
// load locked.
|
||||||
bool success = false;
|
bool success = false;
|
||||||
|
|
4
src/mem/cache/cache_impl.hh
vendored
4
src/mem/cache/cache_impl.hh
vendored
|
@ -180,7 +180,7 @@ Cache<TagStore>::satisfyCpuSideRequest(PacketPtr pkt, BlkType *blk)
|
||||||
pkt->writeDataToBlock(blk->data, blkSize);
|
pkt->writeDataToBlock(blk->data, blkSize);
|
||||||
}
|
}
|
||||||
} else if (pkt->isRead()) {
|
} else if (pkt->isRead()) {
|
||||||
if (pkt->isLocked()) {
|
if (pkt->isLlsc()) {
|
||||||
blk->trackLoadLocked(pkt);
|
blk->trackLoadLocked(pkt);
|
||||||
}
|
}
|
||||||
pkt->setDataFromBlock(blk->data, blkSize);
|
pkt->setDataFromBlock(blk->data, blkSize);
|
||||||
|
@ -317,7 +317,7 @@ Cache<TagStore>::access(PacketPtr pkt, BlkType *&blk,
|
||||||
|
|
||||||
incMissCount(pkt);
|
incMissCount(pkt);
|
||||||
|
|
||||||
if (blk == NULL && pkt->isLocked() && pkt->isWrite()) {
|
if (blk == NULL && pkt->isLlsc() && pkt->isWrite()) {
|
||||||
// complete miss on store conditional... just give up now
|
// complete miss on store conditional... just give up now
|
||||||
pkt->req->setExtraData(0);
|
pkt->req->setExtraData(0);
|
||||||
return true;
|
return true;
|
||||||
|
|
|
@ -105,14 +105,14 @@ MemCmd::commandInfo[] =
|
||||||
InvalidCmd, "ReadExResp" },
|
InvalidCmd, "ReadExResp" },
|
||||||
/* LoadLockedReq: note that we use plain ReadResp as response, so that
|
/* LoadLockedReq: note that we use plain ReadResp as response, so that
|
||||||
* we can also use ReadRespWithInvalidate when needed */
|
* we can also use ReadRespWithInvalidate when needed */
|
||||||
{ SET4(IsRead, IsLocked, IsRequest, NeedsResponse),
|
{ SET4(IsRead, IsLlsc, IsRequest, NeedsResponse),
|
||||||
ReadResp, "LoadLockedReq" },
|
ReadResp, "LoadLockedReq" },
|
||||||
/* StoreCondReq */
|
/* StoreCondReq */
|
||||||
{ SET6(IsWrite, NeedsExclusive, IsLocked,
|
{ SET6(IsWrite, NeedsExclusive, IsLlsc,
|
||||||
IsRequest, NeedsResponse, HasData),
|
IsRequest, NeedsResponse, HasData),
|
||||||
StoreCondResp, "StoreCondReq" },
|
StoreCondResp, "StoreCondReq" },
|
||||||
/* StoreCondResp */
|
/* StoreCondResp */
|
||||||
{ SET4(IsWrite, NeedsExclusive, IsLocked, IsResponse),
|
{ SET4(IsWrite, NeedsExclusive, IsLlsc, IsResponse),
|
||||||
InvalidCmd, "StoreCondResp" },
|
InvalidCmd, "StoreCondResp" },
|
||||||
/* SwapReq -- for Swap ldstub type operations */
|
/* SwapReq -- for Swap ldstub type operations */
|
||||||
{ SET6(IsRead, IsWrite, NeedsExclusive, IsRequest, HasData, NeedsResponse),
|
{ SET6(IsRead, IsWrite, NeedsExclusive, IsRequest, HasData, NeedsResponse),
|
||||||
|
|
|
@ -120,7 +120,7 @@ class MemCmd
|
||||||
NeedsResponse, //!< Requester needs response from target
|
NeedsResponse, //!< Requester needs response from target
|
||||||
IsSWPrefetch,
|
IsSWPrefetch,
|
||||||
IsHWPrefetch,
|
IsHWPrefetch,
|
||||||
IsLocked, //!< Alpha/MIPS LL or SC access
|
IsLlsc, //!< Alpha/MIPS LL or SC access
|
||||||
HasData, //!< There is an associated payload
|
HasData, //!< There is an associated payload
|
||||||
IsError, //!< Error response
|
IsError, //!< Error response
|
||||||
IsPrint, //!< Print state matching address (for debugging)
|
IsPrint, //!< Print state matching address (for debugging)
|
||||||
|
@ -166,7 +166,7 @@ class MemCmd
|
||||||
bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
|
bool isInvalidate() const { return testCmdAttrib(IsInvalidate); }
|
||||||
bool hasData() const { return testCmdAttrib(HasData); }
|
bool hasData() const { return testCmdAttrib(HasData); }
|
||||||
bool isReadWrite() const { return isRead() && isWrite(); }
|
bool isReadWrite() const { return isRead() && isWrite(); }
|
||||||
bool isLocked() const { return testCmdAttrib(IsLocked); }
|
bool isLlsc() const { return testCmdAttrib(IsLlsc); }
|
||||||
bool isError() const { return testCmdAttrib(IsError); }
|
bool isError() const { return testCmdAttrib(IsError); }
|
||||||
bool isPrint() const { return testCmdAttrib(IsPrint); }
|
bool isPrint() const { return testCmdAttrib(IsPrint); }
|
||||||
|
|
||||||
|
@ -401,7 +401,7 @@ class Packet : public FastAlloc, public Printable
|
||||||
bool isInvalidate() const { return cmd.isInvalidate(); }
|
bool isInvalidate() const { return cmd.isInvalidate(); }
|
||||||
bool hasData() const { return cmd.hasData(); }
|
bool hasData() const { return cmd.hasData(); }
|
||||||
bool isReadWrite() const { return cmd.isReadWrite(); }
|
bool isReadWrite() const { return cmd.isReadWrite(); }
|
||||||
bool isLocked() const { return cmd.isLocked(); }
|
bool isLlsc() const { return cmd.isLlsc(); }
|
||||||
bool isError() const { return cmd.isError(); }
|
bool isError() const { return cmd.isError(); }
|
||||||
bool isPrint() const { return cmd.isPrint(); }
|
bool isPrint() const { return cmd.isPrint(); }
|
||||||
|
|
||||||
|
|
|
@ -125,7 +125,7 @@ PhysicalMemory::calculateLatency(PacketPtr pkt)
|
||||||
|
|
||||||
|
|
||||||
// Add load-locked to tracking list. Should only be called if the
|
// Add load-locked to tracking list. Should only be called if the
|
||||||
// operation is a load and the LOCKED flag is set.
|
// operation is a load and the LLSC flag is set.
|
||||||
void
|
void
|
||||||
PhysicalMemory::trackLoadLocked(PacketPtr pkt)
|
PhysicalMemory::trackLoadLocked(PacketPtr pkt)
|
||||||
{
|
{
|
||||||
|
@ -162,12 +162,12 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
|
||||||
{
|
{
|
||||||
Request *req = pkt->req;
|
Request *req = pkt->req;
|
||||||
Addr paddr = LockedAddr::mask(req->getPaddr());
|
Addr paddr = LockedAddr::mask(req->getPaddr());
|
||||||
bool isLocked = pkt->isLocked();
|
bool isLlsc = pkt->isLlsc();
|
||||||
|
|
||||||
// Initialize return value. Non-conditional stores always
|
// Initialize return value. Non-conditional stores always
|
||||||
// succeed. Assume conditional stores will fail until proven
|
// succeed. Assume conditional stores will fail until proven
|
||||||
// otherwise.
|
// otherwise.
|
||||||
bool success = !isLocked;
|
bool success = !isLlsc;
|
||||||
|
|
||||||
// Iterate over list. Note that there could be multiple matching
|
// Iterate over list. Note that there could be multiple matching
|
||||||
// records, as more than one context could have done a load locked
|
// records, as more than one context could have done a load locked
|
||||||
|
@ -179,7 +179,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
|
||||||
if (i->addr == paddr) {
|
if (i->addr == paddr) {
|
||||||
// we have a matching address
|
// we have a matching address
|
||||||
|
|
||||||
if (isLocked && i->matchesContext(req)) {
|
if (isLlsc && i->matchesContext(req)) {
|
||||||
// it's a store conditional, and as far as the memory
|
// it's a store conditional, and as far as the memory
|
||||||
// system can tell, the requesting context's lock is
|
// system can tell, the requesting context's lock is
|
||||||
// still valid.
|
// still valid.
|
||||||
|
@ -199,7 +199,7 @@ PhysicalMemory::checkLockedAddrList(PacketPtr pkt)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
if (isLocked) {
|
if (isLlsc) {
|
||||||
req->setExtraData(success ? 1 : 0);
|
req->setExtraData(success ? 1 : 0);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -284,7 +284,7 @@ PhysicalMemory::doAtomicAccess(PacketPtr pkt)
|
||||||
TRACE_PACKET("Read/Write");
|
TRACE_PACKET("Read/Write");
|
||||||
} else if (pkt->isRead()) {
|
} else if (pkt->isRead()) {
|
||||||
assert(!pkt->isWrite());
|
assert(!pkt->isWrite());
|
||||||
if (pkt->isLocked()) {
|
if (pkt->isLlsc()) {
|
||||||
trackLoadLocked(pkt);
|
trackLoadLocked(pkt);
|
||||||
}
|
}
|
||||||
if (pmemAddr)
|
if (pmemAddr)
|
||||||
|
|
|
@ -129,11 +129,11 @@ class PhysicalMemory : public MemObject
|
||||||
Request *req = pkt->req;
|
Request *req = pkt->req;
|
||||||
if (lockedAddrList.empty()) {
|
if (lockedAddrList.empty()) {
|
||||||
// no locked addrs: nothing to check, store_conditional fails
|
// no locked addrs: nothing to check, store_conditional fails
|
||||||
bool isLocked = pkt->isLocked();
|
bool isLlsc = pkt->isLlsc();
|
||||||
if (isLocked) {
|
if (isLlsc) {
|
||||||
req->setExtraData(0);
|
req->setExtraData(0);
|
||||||
}
|
}
|
||||||
return !isLocked; // only do write if not an sc
|
return !isLlsc; // only do write if not an sc
|
||||||
} else {
|
} else {
|
||||||
// iterate over list...
|
// iterate over list...
|
||||||
return checkLockedAddrList(pkt);
|
return checkLockedAddrList(pkt);
|
||||||
|
|
|
@ -62,7 +62,7 @@ class Request : public FastAlloc
|
||||||
/** ASI information for this request if it exists. */
|
/** ASI information for this request if it exists. */
|
||||||
static const FlagsType ASI_BITS = 0x000000FF;
|
static const FlagsType ASI_BITS = 0x000000FF;
|
||||||
/** The request is a Load locked/store conditional. */
|
/** The request is a Load locked/store conditional. */
|
||||||
static const FlagsType LOCKED = 0x00000100;
|
static const FlagsType LLSC = 0x00000100;
|
||||||
/** The virtual address is also the physical address. */
|
/** The virtual address is also the physical address. */
|
||||||
static const FlagsType PHYSICAL = 0x00000200;
|
static const FlagsType PHYSICAL = 0x00000200;
|
||||||
/** The request is an ALPHA VPTE pal access (hw_ld). */
|
/** The request is an ALPHA VPTE pal access (hw_ld). */
|
||||||
|
@ -448,7 +448,7 @@ class Request : public FastAlloc
|
||||||
/** Accessor Function to Check Cacheability. */
|
/** Accessor Function to Check Cacheability. */
|
||||||
bool isUncacheable() const { return flags.isSet(UNCACHEABLE); }
|
bool isUncacheable() const { return flags.isSet(UNCACHEABLE); }
|
||||||
bool isInstRead() const { return flags.isSet(INST_READ); }
|
bool isInstRead() const { return flags.isSet(INST_READ); }
|
||||||
bool isLocked() const { return flags.isSet(LOCKED); }
|
bool isLlsc() const { return flags.isSet(LLSC); }
|
||||||
bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
|
bool isSwap() const { return flags.isSet(MEM_SWAP|MEM_SWAP_COND); }
|
||||||
bool isCondSwap() const { return flags.isSet(MEM_SWAP_COND); }
|
bool isCondSwap() const { return flags.isSet(MEM_SWAP_COND); }
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue