inorder: dyn inst initialization
remove constructors that werent being used (it just gets confusing) use initialization list for all the variables instead of relying on initVars() function
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e0a021005d
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3e1ad73d08
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@ -47,49 +47,45 @@ using namespace std;
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using namespace TheISA;
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using namespace TheISA;
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using namespace ThePipeline;
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using namespace ThePipeline;
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InOrderDynInst::InOrderDynInst(TheISA::ExtMachInst machInst,
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const TheISA::PCState &instPC,
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const TheISA::PCState &_predPC,
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InstSeqNum seq_num, InOrderCPU *cpu)
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: staticInst(machInst, instPC.instAddr()), traceData(NULL), cpu(cpu)
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{
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seqNum = seq_num;
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pc = instPC;
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predPC = _predPC;
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initVars();
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}
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InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
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InOrderDynInst::InOrderDynInst(InOrderCPU *cpu,
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InOrderThreadState *state,
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InOrderThreadState *state,
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InstSeqNum seq_num,
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InstSeqNum seq_num,
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ThreadID tid,
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ThreadID tid,
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unsigned _asid)
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unsigned _asid)
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: traceData(NULL), cpu(cpu)
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: seqNum(seq_num), bdelaySeqNum(0), threadNumber(tid), asid(_asid),
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virtProcNumber(0), staticInst(NULL), traceData(NULL), cpu(cpu),
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thread(state), fault(NoFault), memData(NULL), loadData(0),
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storeData(0), effAddr(0), physEffAddr(0), memReqFlags(0),
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readyRegs(0), pc(0), predPC(0), memAddr(0), nextStage(0),
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memTime(0), splitMemData(NULL), splitMemReq(NULL), totalSize(0),
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split2ndSize(0), split2ndAddr(0), split2ndAccess(false),
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split2ndDataPtr(NULL), split2ndFlags(0), splitInst(false),
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splitFinishCnt(0), split2ndStoreDataPtr(NULL), splitInstSked(false),
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inFrontEnd(true), frontSked(NULL), backSked(NULL),
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squashingStage(0), predictTaken(false), procDelaySlotOnMispred(false),
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fetchMemReq(NULL), dataMemReq(NULL), instEffAddr(0), eaCalcDone(false),
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lqIdx(0), sqIdx(0), instListIt(NULL)
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{
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{
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seqNum = seq_num;
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for(int i = 0; i < MaxInstSrcRegs; i++) {
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thread = state;
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instSrc[i].integer = 0;
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threadNumber = tid;
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instSrc[i].dbl = 0;
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asid = _asid;
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_readySrcRegIdx[i] = false;
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initVars();
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_srcRegIdx[i] = 0;
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}
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}
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InOrderDynInst::InOrderDynInst(StaticInstPtr &_staticInst)
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for(int j = 0; j < MaxInstDestRegs; j++) {
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: seqNum(0), staticInst(_staticInst), traceData(NULL)
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_destRegIdx[j] = 0;
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{
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_prevDestRegIdx[j] = 0;
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initVars();
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}
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}
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++instcount;
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DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
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" (active insts: %i)\n", threadNumber, seqNum, instcount);
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InOrderDynInst::InOrderDynInst()
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: seqNum(0), traceData(NULL), cpu(cpu)
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{
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initVars();
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}
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}
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int InOrderDynInst::instcount = 0;
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int InOrderDynInst::instcount = 0;
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void
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void
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InOrderDynInst::setMachInst(ExtMachInst machInst)
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InOrderDynInst::setMachInst(ExtMachInst machInst)
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{
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{
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@ -133,7 +129,6 @@ InOrderDynInst::initVars()
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memAddrReady = false;
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memAddrReady = false;
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eaCalcDone = false;
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eaCalcDone = false;
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memOpDone = false;
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predictTaken = false;
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predictTaken = false;
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procDelaySlotOnMispred = false;
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procDelaySlotOnMispred = false;
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@ -164,16 +159,10 @@ InOrderDynInst::initVars()
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}
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}
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// Update Instruction Count for this instruction
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// Update Instruction Count for this instruction
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++instcount;
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if (instcount > 100) {
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if (instcount > 100) {
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fatal("Number of Active Instructions in CPU is too high. "
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fatal("Number of Active Instructions in CPU is too high. "
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"(Not Dereferencing Ptrs. Correctly?)\n");
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"(Not Dereferencing Ptrs. Correctly?)\n");
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}
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}
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DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created."
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" (active insts: %i)\n", threadNumber, seqNum, instcount);
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}
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}
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void
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void
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@ -106,17 +106,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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};
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};
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public:
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public:
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/** BaseDynInst constructor given a binary instruction.
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* @param inst The binary instruction.
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* @param PC The PC of the instruction.
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* @param predPC The predicted next PC.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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*/
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InOrderDynInst(ExtMachInst inst, const TheISA::PCState &PC,
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const TheISA::PCState &predPC, InstSeqNum seq_num,
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InOrderCPU *cpu);
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/** BaseDynInst constructor given a binary instruction.
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/** BaseDynInst constructor given a binary instruction.
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* @param seq_num The sequence number of the instruction.
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* @param seq_num The sequence number of the instruction.
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* @param cpu Pointer to the instruction's CPU.
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* @param cpu Pointer to the instruction's CPU.
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@ -125,14 +114,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
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InOrderDynInst(InOrderCPU *cpu, InOrderThreadState *state,
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InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
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InstSeqNum seq_num, ThreadID tid, unsigned asid = 0);
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/** BaseDynInst constructor given a StaticInst pointer.
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* @param _staticInst The StaticInst for this BaseDynInst.
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*/
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InOrderDynInst(StaticInstPtr &_staticInst);
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/** Skeleton Constructor. */
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InOrderDynInst();
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/** InOrderDynInst destructor. */
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/** InOrderDynInst destructor. */
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~InOrderDynInst();
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~InOrderDynInst();
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@ -219,12 +200,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** The effective physical address. */
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/** The effective physical address. */
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Addr physEffAddr;
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Addr physEffAddr;
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/** Effective virtual address for a copy source. */
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Addr copySrcEffAddr;
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/** Effective physical address for a copy source. */
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Addr copySrcPhysEffAddr;
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/** The memory request flags (from translation). */
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/** The memory request flags (from translation). */
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unsigned memReqFlags;
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unsigned memReqFlags;
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@ -253,8 +228,11 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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Tick tick;
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Tick tick;
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InstResult()
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InstResult()
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: type(None), tick(0)
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: type(None), tick(0)
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{}
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{
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val.integer = 0;
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val.dbl = 0;
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}
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};
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};
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/** The source of the instruction; assumes for now that there's only one
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/** The source of the instruction; assumes for now that there's only one
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@ -273,10 +251,8 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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/** Predicted next PC. */
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/** Predicted next PC. */
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TheISA::PCState predPC;
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TheISA::PCState predPC;
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/** Address to fetch from */
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Addr fetchAddr;
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/** Address to get/write data from/to */
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/** Address to get/write data from/to */
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/* Fetching address when inst. starts, Data address for load/store after fetch*/
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Addr memAddr;
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Addr memAddr;
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/** Whether or not the source register is ready.
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/** Whether or not the source register is ready.
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@ -477,7 +453,9 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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curSkedEntry++;
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curSkedEntry++;
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if (inFrontEnd && curSkedEntry == frontSked_end) {
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if (inFrontEnd && curSkedEntry == frontSked_end) {
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assert(backSked != NULL);
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DPRINTF(InOrderDynInst, "[sn:%i] Switching to "
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"back end schedule.\n", seqNum);
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assert(backSked != NULL);
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curSkedEntry.init(backSked);
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curSkedEntry.init(backSked);
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curSkedEntry = backSked->begin();
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curSkedEntry = backSked->begin();
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inFrontEnd = false;
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inFrontEnd = false;
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@ -485,6 +463,10 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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return true;
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return true;
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}
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}
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DPRINTF(InOrderDynInst, "[sn:%i] Next Stage: %i "
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"Next Resource: %i.\n", seqNum, curSkedEntry->stageNum,
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curSkedEntry->resNum);
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return false;
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return false;
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}
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}
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@ -996,10 +978,6 @@ class InOrderDynInst : public FastAlloc, public RefCounted
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*/
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*/
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bool eaCalcDone;
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bool eaCalcDone;
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public:
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/** Whether or not the memory operation is done. */
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bool memOpDone;
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public:
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public:
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/** Load queue index. */
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/** Load queue index. */
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int16_t lqIdx;
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int16_t lqIdx;
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