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Merge zizzer:/z/m5/Bitkeeper/m5

Browse source 
into zizzer.eecs.umich.edu:/.automount/zazzer/z/rdreslin/m5bk/timing_L1

--HG--
extra : convert_revision : 0b0583e9404ed922141049f1043e7a149984e567
This commit is contained in:
Ron Dreslinski 2005-02-21 18:07:30 -05:00
commit 3e18c75f00
3 changed files with 51 additions and 56 deletions
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7
dev/tsunami.hh
View file

@ -32,8 +32,8 @@
* retains pointers to all its children so the children can communicate. * retains pointers to all its children so the children can communicate.
*/ */
#ifndef __TSUNAMI_HH__ #ifndef __DEV_TSUNAMI_HH__
#define __TSUNAMI_HH__ #define __DEV_TSUNAMI_HH__
#include "dev/platform.hh" #include "dev/platform.hh"
@ -56,7 +56,6 @@ class System;
class Tsunami : public Platform class Tsunami : public Platform
{ {
public: public:
/** Max number of CPUs in a Tsunami */ /** Max number of CPUs in a Tsunami */
static const int Max_CPUs = 64; static const int Max_CPUs = 64;
@ -134,4 +133,4 @@ class Tsunami : public Platform
virtual void unserialize(Checkpoint *cp, const std::string &section); virtual void unserialize(Checkpoint *cp, const std::string &section);
}; };
#endif // __TSUNAMI_HH__ #endif // __DEV_TSUNAMI_HH__

1
dev/tsunami_io.cc
View file

@ -67,7 +67,6 @@ TsunamiIO::RTCEvent::process()
schedule(curTick + ticksPerSecond/RTC_RATE); schedule(curTick + ticksPerSecond/RTC_RATE);
//Actually interrupt the processor here //Actually interrupt the processor here
tsunami->cchip->postRTC(); tsunami->cchip->postRTC();
} }
const char * const char *

21
dev/tsunami_io.hh
View file

@ -30,8 +30,8 @@
* Tsunami Fake I/O Space mapping including RTC/timer interrupts * Tsunami Fake I/O Space mapping including RTC/timer interrupts
*/ */
#ifndef __TSUNAMI_DMA_HH__ #ifndef __DEV_TSUNAMI_IO_HH__
#define __TSUNAMI_DMA_HH__ #define __DEV_TSUNAMI_IO_HH__
#include "dev/io_device.hh" #include "dev/io_device.hh"
#include "base/range.hh" #include "base/range.hh"
@ -56,9 +56,11 @@ class TsunamiIO : public PioDevice
struct tm tm; struct tm tm;
/** In Tsunami RTC only has two i/o ports one for data and one for address, /**
* so you write the address and then read/write the data. This store the * In Tsunami RTC only has two i/o ports one for data and one for
* address you are going to be reading from on a read. * address, so you write the address and then read/write the
* data. This store the address you are going to be reading from
* on a read.
*/ */
uint8_t RTCAddress; uint8_t RTCAddress;
@ -141,7 +143,7 @@ class TsunamiIO : public PioDevice
/** /**
* Interrupth the processor and reschedule the event. * Interrupth the processor and reschedule the event.
* */ */
virtual void process(); virtual void process();
/** /**
@ -156,7 +158,6 @@ class TsunamiIO : public PioDevice
*/ */
virtual void serialize(std::ostream &os); virtual void serialize(std::ostream &os);
/** /**
* Reconstruct the state of this object from a checkpoint. * Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use. * @param cp The checkpoint use.
@ -219,7 +220,6 @@ class TsunamiIO : public PioDevice
*/ */
uint32_t timerData; uint32_t timerData;
public: public:
/** /**
* Return the freqency of the RTC * Return the freqency of the RTC
@ -227,7 +227,6 @@ class TsunamiIO : public PioDevice
*/ */
Tick frequency() const { return RTC_RATE; } Tick frequency() const { return RTC_RATE; }
/** /**
* Initialize all the data for devices supported by Tsunami I/O. * Initialize all the data for devices supported by Tsunami I/O.
* @param name name of this device. * @param name name of this device.
@ -279,7 +278,6 @@ class TsunamiIO : public PioDevice
*/ */
virtual void serialize(std::ostream &os); virtual void serialize(std::ostream &os);
/** /**
* Reconstruct the state of this object from a checkpoint. * Reconstruct the state of this object from a checkpoint.
* @param cp The checkpoint use. * @param cp The checkpoint use.
@ -287,8 +285,7 @@ class TsunamiIO : public PioDevice
*/ */
virtual void unserialize(Checkpoint *cp, const std::string &section); virtual void unserialize(Checkpoint *cp, const std::string &section);
Tick cacheAccess(MemReqPtr &req); Tick cacheAccess(MemReqPtr &req);
}; };
#endif // __TSUNAMI_IO_HH__ #endif // __DEV_TSUNAMI_IO_HH__