diff --git a/configs/example/fs.py b/configs/example/fs.py
index f1b8acedf..9b8ae1d29 100644
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -139,6 +139,7 @@ for i in xrange(np):
         test_sys.cpu[i].fastmem = True
     if options.checker:
         test_sys.cpu[i].addCheckerCpu()
+    test_sys.cpu[i].createThreads()
 
 CacheConfig.config_cache(options, test_sys)
 
@@ -155,6 +156,7 @@ if len(bm) == 2:
         drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
 
     drive_sys.cpu = DriveCPUClass(cpu_id=0)
+    drive_sys.cpu.createThreads()
     drive_sys.cpu.createInterruptController()
     drive_sys.cpu.connectAllPorts(drive_sys.membus)
     if options.fastmem:
diff --git a/configs/example/ruby_fs.py b/configs/example/ruby_fs.py
index 97863a46b..8d21cfb32 100644
--- a/configs/example/ruby_fs.py
+++ b/configs/example/ruby_fs.py
@@ -103,6 +103,7 @@ for (i, cpu) in enumerate(system.cpu):
     #
     # Tie the cpu ports to the correct ruby system ports
     #
+    cpu.createThreads()
     cpu.createInterruptController()
     cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
     cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
diff --git a/configs/example/se.py b/configs/example/se.py
index c4c6daedf..fe5524ef5 100644
--- a/configs/example/se.py
+++ b/configs/example/se.py
@@ -180,6 +180,8 @@ for i in xrange(np):
     if options.checker:
         system.cpu[i].addCheckerCpu()
 
+    system.cpu[i].createThreads()
+
 if options.ruby:
     if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
         print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
diff --git a/src/arch/alpha/AlphaISA.py b/src/arch/alpha/AlphaISA.py
new file mode 100644
index 000000000..64c9e4733
--- /dev/null
+++ b/src/arch/alpha/AlphaISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class AlphaISA(SimObject):
+    type = 'AlphaISA'
+    cxx_class = 'AlphaISA::ISA'
+    cxx_header = "arch/alpha/isa.hh"
diff --git a/src/arch/alpha/SConscript b/src/arch/alpha/SConscript
index 421040bb5..f099c5e25 100644
--- a/src/arch/alpha/SConscript
+++ b/src/arch/alpha/SConscript
@@ -59,6 +59,7 @@ if env['TARGET_ISA'] == 'alpha':
     Source('vtophys.cc')
 
     SimObject('AlphaInterrupts.py')
+    SimObject('AlphaISA.py')
     SimObject('AlphaSystem.py')
     SimObject('AlphaTLB.py')
 
diff --git a/src/arch/alpha/isa.cc b/src/arch/alpha/isa.cc
index 5fd34a492..f5660e4f2 100644
--- a/src/arch/alpha/isa.cc
+++ b/src/arch/alpha/isa.cc
@@ -33,11 +33,25 @@
 #include "arch/alpha/isa.hh"
 #include "base/misc.hh"
 #include "cpu/thread_context.hh"
+#include "params/AlphaISA.hh"
 #include "sim/serialize.hh"
 
 namespace AlphaISA
 {
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+    initializeIprTable();
+}
+
+const AlphaISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::serialize(EventManager *em, std::ostream &os)
 {
@@ -151,3 +165,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc,
 }
 
 }
+
+AlphaISA::ISA *
+AlphaISAParams::create()
+{
+    return new AlphaISA::ISA(this);
+}
diff --git a/src/arch/alpha/isa.hh b/src/arch/alpha/isa.hh
index f1bfcebec..4e22c7eea 100644
--- a/src/arch/alpha/isa.hh
+++ b/src/arch/alpha/isa.hh
@@ -38,7 +38,9 @@
 #include "arch/alpha/registers.hh"
 #include "arch/alpha/types.hh"
 #include "base/types.hh"
+#include "sim/sim_object.hh"
 
+struct AlphaISAParams;
 class BaseCPU;
 class Checkpoint;
 class EventManager;
@@ -46,10 +48,11 @@ class ThreadContext;
 
 namespace AlphaISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         typedef uint64_t InternalProcReg;
+        typedef AlphaISAParams Params;
 
       protected:
         uint64_t fpcr;       // floating point condition codes
@@ -101,11 +104,9 @@ namespace AlphaISA
             return reg;
         }
 
-        ISA()
-        {
-            clear();
-            initializeIprTable();
-        }
+        const Params *params() const;
+
+        ISA(Params *p);
     };
 }
 
diff --git a/src/arch/arm/ArmISA.py b/src/arch/arm/ArmISA.py
new file mode 100644
index 000000000..fc291cfc1
--- /dev/null
+++ b/src/arch/arm/ArmISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class ArmISA(SimObject):
+    type = 'ArmISA'
+    cxx_class = 'ArmISA::ISA'
+    cxx_header = "arch/arm/isa.hh"
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 44b6286a0..8d13a9b2d 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -72,6 +72,7 @@ if env['TARGET_ISA'] == 'arm':
     Source('vtophys.cc')
 
     SimObject('ArmInterrupts.py')
+    SimObject('ArmISA.py')
     SimObject('ArmNativeTrace.py')
     SimObject('ArmSystem.py')
     SimObject('ArmTLB.py')
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ee2799147..24baa4b0e 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -43,6 +43,7 @@
 #include "cpu/checker/cpu.hh"
 #include "debug/Arm.hh"
 #include "debug/MiscRegs.hh"
+#include "params/ArmISA.hh"
 #include "sim/faults.hh"
 #include "sim/stat_control.hh"
 #include "sim/system.hh"
@@ -50,6 +51,21 @@
 namespace ArmISA
 {
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    SCTLR sctlr;
+    sctlr = 0;
+    miscRegs[MISCREG_SCTLR_RST] = sctlr;
+    clear();
+}
+
+const ArmISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::clear()
 {
@@ -641,3 +657,9 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
 }
 
 }
+
+ArmISA::ISA *
+ArmISAParams::create()
+{
+    return new ArmISA::ISA(this);
+}
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 48840bf07..9701ce10e 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -47,14 +47,16 @@
 #include "arch/arm/tlb.hh"
 #include "arch/arm/types.hh"
 #include "debug/Checkpoint.hh"
+#include "sim/sim_object.hh"
 
+struct ArmISAParams;
 class ThreadContext;
 class Checkpoint;
 class EventManager;
 
 namespace ArmISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
         MiscReg miscRegs[NumMiscRegs];
@@ -192,14 +194,11 @@ namespace ArmISA
             updateRegMap(tmp_cpsr);
         }
 
-        ISA()
-        {
-            SCTLR sctlr;
-            sctlr = 0;
-            miscRegs[MISCREG_SCTLR_RST] = sctlr;
+        typedef ArmISAParams Params;
 
-            clear();
-        }
+        const Params *params() const;
+
+        ISA(Params *p);
     };
 }
 
diff --git a/src/arch/mips/MipsISA.py b/src/arch/mips/MipsISA.py
new file mode 100644
index 000000000..bc969a906
--- /dev/null
+++ b/src/arch/mips/MipsISA.py
@@ -0,0 +1,47 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+from m5.params import *
+
+class MipsISA(SimObject):
+    type = 'MipsISA'
+    cxx_class = 'MipsISA::ISA'
+    cxx_header = "arch/mips/isa.hh"
+
+    num_threads = Param.UInt8(1, "Maximum number this ISA can handle")
+    num_vpes = Param.UInt8(1, "Maximum number of vpes this ISA can handle")
diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript
index 15b4ffc51..944fc8e55 100644
--- a/src/arch/mips/SConscript
+++ b/src/arch/mips/SConscript
@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'mips':
     Source('vtophys.cc')
 
     SimObject('MipsInterrupts.py')
+    SimObject('MipsISA.py')
     SimObject('MipsSystem.py')
     SimObject('MipsTLB.py')
 
diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc
index f6de102cd..891ed5e2f 100644
--- a/src/arch/mips/isa.cc
+++ b/src/arch/mips/isa.cc
@@ -36,6 +36,7 @@
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
 #include "debug/MipsPRA.hh"
+#include "params/MipsISA.hh"
 
 namespace MipsISA
 {
@@ -87,11 +88,10 @@ ISA::miscRegNames[NumMiscRegs] =
     "LLFlag"
 };
 
-ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
+ISA::ISA(Params *p)
+    : SimObject(p),
+      numThreads(p->num_threads), numVpes(p->num_vpes)
 {
-    numThreads = num_threads;
-    numVpes = num_vpes;
-
     miscRegFile.resize(NumMiscRegs);
     bankType.resize(NumMiscRegs);
 
@@ -142,6 +142,12 @@ ISA::ISA(uint8_t num_threads, uint8_t num_vpes)
     clear();
 }
 
+const MipsISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::clear()
 {
@@ -586,3 +592,9 @@ ISA::CP0Event::unscheduleEvent()
 }
 
 }
+
+MipsISA::ISA *
+MipsISAParams::create()
+{
+    return new MipsISA::ISA(this);
+}
diff --git a/src/arch/mips/isa.hh b/src/arch/mips/isa.hh
index a313b4382..3f4477132 100644
--- a/src/arch/mips/isa.hh
+++ b/src/arch/mips/isa.hh
@@ -39,20 +39,24 @@
 #include "arch/mips/types.hh"
 #include "sim/eventq.hh"
 #include "sim/fault_fwd.hh"
+#include "sim/sim_object.hh"
 
 class BaseCPU;
 class Checkpoint;
 class EventManager;
+struct MipsISAParams;
 class ThreadContext;
 
 namespace MipsISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       public:
         // The MIPS name for this file is CP0 or Coprocessor 0
         typedef ISA CP0;
 
+        typedef MipsISAParams Params;
+
       protected:
         // Number of threads and vpes an individual ISA state can handle
         uint8_t numThreads;
@@ -69,8 +73,6 @@ namespace MipsISA
         std::vector<BankType> bankType;
 
       public:
-        ISA(uint8_t num_threads = 1, uint8_t num_vpes = 1);
-
         void clear();
 
         void configCP();
@@ -155,6 +157,9 @@ namespace MipsISA
         static std::string miscRegNames[NumMiscRegs];
 
       public:
+        const Params *params() const;
+
+        ISA(Params *p);
 
         int
         flattenIntIndex(int reg)
diff --git a/src/arch/power/PowerISA.py b/src/arch/power/PowerISA.py
new file mode 100644
index 000000000..df35ab359
--- /dev/null
+++ b/src/arch/power/PowerISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class PowerISA(SimObject):
+    type = 'PowerISA'
+    cxx_class = 'PowerISA::ISA'
+    cxx_header = "arch/power/isa.hh"
diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript
index a9d20b4bd..f7875cdf5 100644
--- a/src/arch/power/SConscript
+++ b/src/arch/power/SConscript
@@ -44,6 +44,7 @@ if env['TARGET_ISA'] == 'power':
     Source('interrupts.cc')
     Source('linux/linux.cc')
     Source('linux/process.cc')
+    Source('isa.cc')
     Source('pagetable.cc')
     Source('process.cc')
     Source('stacktrace.cc')
@@ -52,6 +53,7 @@ if env['TARGET_ISA'] == 'power':
     Source('vtophys.cc')
 
     SimObject('PowerInterrupts.py')
+    SimObject('PowerISA.py')
     SimObject('PowerTLB.py')
 
     DebugFlag('Power')
diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc
new file mode 100644
index 000000000..0b49c9714
--- /dev/null
+++ b/src/arch/power/isa.cc
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2012 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Sandberg
+ */
+
+#include "arch/power/isa.hh"
+#include "params/PowerISA.hh"
+
+namespace PowerISA
+{
+
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+}
+
+const PowerISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
+}
+
+PowerISA::ISA *
+PowerISAParams::create()
+{
+    return new PowerISA::ISA(this);
+}
+
diff --git a/src/arch/power/isa.hh b/src/arch/power/isa.hh
index 78ae18ea9..446f918f1 100644
--- a/src/arch/power/isa.hh
+++ b/src/arch/power/isa.hh
@@ -36,7 +36,9 @@
 #include "arch/power/registers.hh"
 #include "arch/power/types.hh"
 #include "base/misc.hh"
+#include "sim/sim_object.hh"
 
+struct PowerISAParams;
 class ThreadContext;
 class Checkpoint;
 class EventManager;
@@ -44,13 +46,15 @@ class EventManager;
 namespace PowerISA
 {
 
-class ISA
+class ISA : public SimObject
 {
   protected:
     MiscReg dummy;
     MiscReg miscRegs[NumMiscRegs];
 
   public:
+    typedef PowerISAParams Params;
+
     void
     clear()
     {
@@ -104,10 +108,9 @@ class ISA
     {
     }
 
-    ISA()
-    {
-        clear();
-    }
+    const Params *params() const;
+
+    ISA(Params *p);
 };
 
 } // namespace PowerISA
diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 5e2146750..28949aaaf 100644
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -53,6 +53,7 @@ if env['TARGET_ISA'] == 'sparc':
     Source('vtophys.cc')
 
     SimObject('SparcInterrupts.py')
+    SimObject('SparcISA.py')
     SimObject('SparcNativeTrace.py')
     SimObject('SparcSystem.py')
     SimObject('SparcTLB.py')
diff --git a/src/arch/sparc/SparcISA.py b/src/arch/sparc/SparcISA.py
new file mode 100644
index 000000000..23776f673
--- /dev/null
+++ b/src/arch/sparc/SparcISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class SparcISA(SimObject):
+    type = 'SparcISA'
+    cxx_class = 'SparcISA::ISA'
+    cxx_header = "arch/sparc/isa.hh"
diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc
index b8b4e88cc..0c7e83e8e 100644
--- a/src/arch/sparc/isa.cc
+++ b/src/arch/sparc/isa.cc
@@ -37,6 +37,7 @@
 #include "cpu/thread_context.hh"
 #include "debug/MiscRegs.hh"
 #include "debug/Timer.hh"
+#include "params/SparcISA.hh"
 
 namespace SparcISA
 {
@@ -58,6 +59,22 @@ buildPstateMask()
 
 static const PSTATE PstateMask = buildPstateMask();
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    tickCompare = NULL;
+    sTickCompare = NULL;
+    hSTickCompare = NULL;
+
+    clear();
+}
+
+const SparcISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 void
 ISA::reloadRegMap()
 {
@@ -780,3 +797,9 @@ ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string &section)
 }
 
 }
+
+SparcISA::ISA *
+SparcISAParams::create()
+{
+    return new SparcISA::ISA(this);
+}
diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index 713f01fa5..654cb3507 100644
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -37,14 +37,16 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
+struct SparcISAParams;
 class ThreadContext;
 
 namespace SparcISA
 {
-class ISA
+class ISA : public SimObject
 {
   private:
 
@@ -200,14 +202,10 @@ class ISA
         return reg;
     }
 
-    ISA()
-    {
-        tickCompare = NULL;
-        sTickCompare = NULL;
-        hSTickCompare = NULL;
+    typedef SparcISAParams Params;
+    const Params *params() const;
 
-        clear();
-    }
+    ISA(Params *p);
 };
 }
 
diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript
index 92b30ced1..6ec714e8e 100644
--- a/src/arch/x86/SConscript
+++ b/src/arch/x86/SConscript
@@ -73,6 +73,7 @@ if env['TARGET_ISA'] == 'x86':
     Source('utility.cc')
     Source('vtophys.cc')
 
+    SimObject('X86ISA.py')
     SimObject('X86LocalApic.py')
     SimObject('X86NativeTrace.py')
     SimObject('X86System.py')
diff --git a/src/arch/x86/X86ISA.py b/src/arch/x86/X86ISA.py
new file mode 100644
index 000000000..75d8e85c9
--- /dev/null
+++ b/src/arch/x86/X86ISA.py
@@ -0,0 +1,43 @@
+# Copyright (c) 2012 ARM Limited
+# All rights reserved.
+#
+# The license below extends only to copyright in the software and shall
+# not be construed as granting a license to any other intellectual
+# property including but not limited to intellectual property relating
+# to a hardware implementation of the functionality of the software
+# licensed hereunder.  You may use the software subject to the license
+# terms below provided that you ensure that this notice is replicated
+# unmodified and in its entirety in all distributions of the software,
+# modified or unmodified, in source code or in binary form.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+# Authors: Andreas Sandberg
+
+from m5.SimObject import SimObject
+
+class X86ISA(SimObject):
+    type = 'X86ISA'
+    cxx_class = 'X86ISA::ISA'
+    cxx_header = "arch/x86/isa.hh"
diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc
index 1a9b39840..9dbab8c7e 100644
--- a/src/arch/x86/isa.cc
+++ b/src/arch/x86/isa.cc
@@ -33,6 +33,7 @@
 #include "arch/x86/tlb.hh"
 #include "cpu/base.hh"
 #include "cpu/thread_context.hh"
+#include "params/X86ISA.hh"
 #include "sim/serialize.hh"
 
 namespace X86ISA
@@ -110,6 +111,18 @@ ISA::clear()
     regVal[MISCREG_DR7] = 1 << 10;
 }
 
+ISA::ISA(Params *p)
+    : SimObject(p)
+{
+    clear();
+}
+
+const X86ISAParams *
+ISA::params() const
+{
+    return dynamic_cast<const Params *>(_params);
+}
+
 MiscReg
 ISA::readMiscRegNoEffect(int miscReg)
 {
@@ -376,3 +389,9 @@ ISA::unserialize(EventManager *em, Checkpoint * cp,
 }
 
 }
+
+X86ISA::ISA *
+X86ISAParams::create()
+{
+    return new X86ISA::ISA(this);
+}
diff --git a/src/arch/x86/isa.hh b/src/arch/x86/isa.hh
index 7b0c7b61a..39ed68ea5 100644
--- a/src/arch/x86/isa.hh
+++ b/src/arch/x86/isa.hh
@@ -38,14 +38,16 @@
 #include "arch/x86/regs/misc.hh"
 #include "arch/x86/registers.hh"
 #include "base/types.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
 class ThreadContext;
+struct X86ISAParams;
 
 namespace X86ISA
 {
-    class ISA
+    class ISA : public SimObject
     {
       protected:
         MiscReg regVal[NUM_MISCREGS];
@@ -54,12 +56,12 @@ namespace X86ISA
                 ThreadContext *tc);
 
       public:
+        typedef X86ISAParams Params;
+
         void clear();
 
-        ISA()
-        {
-            clear();
-        }
+        ISA(Params *p);
+        const Params *params() const;
 
         MiscReg readMiscRegNoEffect(int miscReg);
         MiscReg readMiscReg(int miscReg, ThreadContext *tc);
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index dfbd459fd..697be87e1 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -57,21 +57,33 @@ default_tracer = ExeTracer()
 if buildEnv['TARGET_ISA'] == 'alpha':
     from AlphaTLB import AlphaDTB, AlphaITB
     from AlphaInterrupts import AlphaInterrupts
+    from AlphaISA import AlphaISA
+    isa_class = AlphaISA
 elif buildEnv['TARGET_ISA'] == 'sparc':
     from SparcTLB import SparcTLB
     from SparcInterrupts import SparcInterrupts
+    from SparcISA import SparcISA
+    isa_class = SparcISA
 elif buildEnv['TARGET_ISA'] == 'x86':
     from X86TLB import X86TLB
     from X86LocalApic import X86LocalApic
+    from X86ISA import X86ISA
+    isa_class = X86ISA
 elif buildEnv['TARGET_ISA'] == 'mips':
     from MipsTLB import MipsTLB
     from MipsInterrupts import MipsInterrupts
+    from MipsISA import MipsISA
+    isa_class = MipsISA
 elif buildEnv['TARGET_ISA'] == 'arm':
     from ArmTLB import ArmTLB
     from ArmInterrupts import ArmInterrupts
+    from ArmISA import ArmISA
+    isa_class = ArmISA
 elif buildEnv['TARGET_ISA'] == 'power':
     from PowerTLB import PowerTLB
     from PowerInterrupts import PowerInterrupts
+    from PowerISA import PowerISA
+    isa_class = PowerISA
 
 class BaseCPU(MemObject):
     type = 'BaseCPU'
@@ -113,31 +125,37 @@ class BaseCPU(MemObject):
         itb = Param.SparcTLB(SparcTLB(), "Instruction TLB")
         interrupts = Param.SparcInterrupts(
                 NULL, "Interrupt Controller")
+        isa = VectorParam.SparcISA([ isa_class() ], "ISA instance")
     elif buildEnv['TARGET_ISA'] == 'alpha':
         dtb = Param.AlphaTLB(AlphaDTB(), "Data TLB")
         itb = Param.AlphaTLB(AlphaITB(), "Instruction TLB")
         interrupts = Param.AlphaInterrupts(
                 NULL, "Interrupt Controller")
+        isa = VectorParam.AlphaISA([ isa_class() ], "ISA instance")
     elif buildEnv['TARGET_ISA'] == 'x86':
         dtb = Param.X86TLB(X86TLB(), "Data TLB")
         itb = Param.X86TLB(X86TLB(), "Instruction TLB")
         interrupts = Param.X86LocalApic(NULL, "Interrupt Controller")
+        isa = VectorParam.X86ISA([ isa_class() ], "ISA instance")
     elif buildEnv['TARGET_ISA'] == 'mips':
         dtb = Param.MipsTLB(MipsTLB(), "Data TLB")
         itb = Param.MipsTLB(MipsTLB(), "Instruction TLB")
         interrupts = Param.MipsInterrupts(
                 NULL, "Interrupt Controller")
+        isa = VectorParam.MipsISA([ isa_class() ], "ISA instance")
     elif buildEnv['TARGET_ISA'] == 'arm':
         dtb = Param.ArmTLB(ArmTLB(), "Data TLB")
         itb = Param.ArmTLB(ArmTLB(), "Instruction TLB")
         interrupts = Param.ArmInterrupts(
                 NULL, "Interrupt Controller")
+        isa = VectorParam.ArmISA([ isa_class() ], "ISA instance")
     elif buildEnv['TARGET_ISA'] == 'power':
         UnifiedTLB = Param.Bool(True, "Is this a Unified TLB?")
         dtb = Param.PowerTLB(PowerTLB(), "Data TLB")
         itb = Param.PowerTLB(PowerTLB(), "Instruction TLB")
         interrupts = Param.PowerInterrupts(
                 NULL, "Interrupt Controller")
+        isa = VectorParam.PowerISA([ isa_class() ], "ISA instance")
     else:
         print "Don't know what TLB to use for ISA %s" % \
             buildEnv['TARGET_ISA']
@@ -241,5 +259,10 @@ class BaseCPU(MemObject):
         self.toL2Bus.master = self.l2cache.cpu_side
         self._cached_ports = ['l2cache.mem_side']
 
+    def createThreads(self):
+        self.isa = [ isa_class() for i in xrange(self.numThreads) ]
+        if self.checker != NULL:
+            self.checker.createThreads()
+
     def addCheckerCpu(self):
         pass
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index aaf9c9cbc..2b1df6696 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -230,6 +230,11 @@ BaseCPU::BaseCPU(Params *p, bool is_checker)
             profileEvent = new ProfileEvent(this, params()->profile);
     }
     tracer = params()->tracer;
+
+    if (params()->isa.size() != numThreads) {
+        fatal("Number of ISAs (%i) assigned to the CPU does not equal number "
+              "of threads (%i).\n", params()->isa.size(), numThreads);
+    }
 }
 
 void
diff --git a/src/cpu/checker/cpu.cc b/src/cpu/checker/cpu.cc
index 3c1690ac3..f695c24df 100644
--- a/src/cpu/checker/cpu.cc
+++ b/src/cpu/checker/cpu.cc
@@ -96,14 +96,17 @@ CheckerCPU::~CheckerCPU()
 void
 CheckerCPU::setSystem(System *system)
 {
+    const Params *p(dynamic_cast<const Params *>(_params));
+
     systemPtr = system;
 
     if (FullSystem) {
-        thread = new SimpleThread(this, 0, systemPtr, itb, dtb, false);
+        thread = new SimpleThread(this, 0, systemPtr, itb, dtb,
+                                  p->isa[0], false);
     } else {
         thread = new SimpleThread(this, 0, systemPtr,
                                   workload.size() ? workload[0] : NULL,
-                                  itb, dtb);
+                                  itb, dtb, p->isa[0]);
     }
 
     tc = thread->getTC();
diff --git a/src/cpu/dummy_checker.cc b/src/cpu/dummy_checker.cc
index 6a0210e3b..7a5b46e43 100644
--- a/src/cpu/dummy_checker.cc
+++ b/src/cpu/dummy_checker.cc
@@ -69,6 +69,7 @@ DummyCheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/inorder/cpu.cc b/src/cpu/inorder/cpu.cc
index 5815775f9..1ca0657ad 100644
--- a/src/cpu/inorder/cpu.cc
+++ b/src/cpu/inorder/cpu.cc
@@ -230,6 +230,7 @@ InOrderCPU::InOrderCPU(Params *params)
       tickEvent(this),
       stageWidth(params->stageWidth),
       resPool(new ResourcePool(this, params)),
+      isa(numThreads, NULL),
       timeBuffer(2 , 2),
       dataPort(resPool->getDataUnit(), ".dcache_port"),
       instPort(resPool->getInstUnit(), ".icache_port"),
@@ -280,6 +281,7 @@ InOrderCPU::InOrderCPU(Params *params)
     }
 
     for (ThreadID tid = 0; tid < numThreads; ++tid) {
+        isa[tid] = params->isa[tid];
         pc[tid].set(0);
         lastCommittedPC[tid].set(0);
 
@@ -358,7 +360,7 @@ InOrderCPU::InOrderCPU(Params *params)
 
         memset(intRegs[tid], 0, sizeof(intRegs[tid]));
         memset(floatRegs.i[tid], 0, sizeof(floatRegs.i[tid]));
-        isa[tid].clear();
+        isa[tid]->clear();
 
         // Define dummy instructions and resource requests to be used.
         dummyInst[tid] = new InOrderDynInst(this, 
@@ -1249,11 +1251,11 @@ InOrderCPU::flattenRegIdx(RegIndex reg_idx, RegType &reg_type, ThreadID tid)
 {
     if (reg_idx < FP_Base_DepTag) {
         reg_type = IntType;
-        return isa[tid].flattenIntIndex(reg_idx);
+        return isa[tid]->flattenIntIndex(reg_idx);
     } else if (reg_idx < Ctrl_Base_DepTag) {
         reg_type = FloatType;
         reg_idx -= FP_Base_DepTag;
-        return isa[tid].flattenFloatIndex(reg_idx);
+        return isa[tid]->flattenFloatIndex(reg_idx);
     } else {
         reg_type = MiscType;
         return reg_idx - TheISA::Ctrl_Base_DepTag;
@@ -1369,25 +1371,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
 MiscReg
 InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return isa[tid].readMiscRegNoEffect(misc_reg);
+    return isa[tid]->readMiscRegNoEffect(misc_reg);
 }
 
 MiscReg
 InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
 {
-    return isa[tid].readMiscReg(misc_reg, tcBase(tid));
+    return isa[tid]->readMiscReg(misc_reg, tcBase(tid));
 }
 
 void
 InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    isa[tid].setMiscRegNoEffect(misc_reg, val);
+    isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 void
 InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
 {
-    isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
+    isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 
diff --git a/src/cpu/inorder/cpu.hh b/src/cpu/inorder/cpu.hh
index a0fe834e8..acdac11d9 100644
--- a/src/cpu/inorder/cpu.hh
+++ b/src/cpu/inorder/cpu.hh
@@ -325,7 +325,7 @@ class InOrderCPU : public BaseCPU
     TheISA::IntReg intRegs[ThePipeline::MaxThreads][TheISA::NumIntRegs];
 
     /** ISA state */
-    TheISA::ISA isa[ThePipeline::MaxThreads];
+    std::vector<TheISA::ISA *> isa;
 
     /** Dependency Tracker for Integer & Floating Point Regs */
     RegDepMap archRegDepMap[ThePipeline::MaxThreads];
diff --git a/src/cpu/inorder/thread_context.cc b/src/cpu/inorder/thread_context.cc
index b8662ef4c..6b3375a52 100644
--- a/src/cpu/inorder/thread_context.cc
+++ b/src/cpu/inorder/thread_context.cc
@@ -173,7 +173,7 @@ InOrderThreadContext::copyArchRegs(ThreadContext *src_tc)
 void
 InOrderThreadContext::clearArchRegs()
 {
-    cpu->isa[thread->threadId()].clear();
+    cpu->isa[thread->threadId()]->clear();
 }
 
 
@@ -181,7 +181,7 @@ uint64_t
 InOrderThreadContext::readIntReg(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
     return cpu->readIntReg(reg_idx, tid);
 }
 
@@ -189,7 +189,7 @@ FloatReg
 InOrderThreadContext::readFloatReg(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     return cpu->readFloatReg(reg_idx, tid);
 }
 
@@ -197,7 +197,7 @@ FloatRegBits
 InOrderThreadContext::readFloatRegBits(int reg_idx)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     return cpu->readFloatRegBits(reg_idx, tid);
 }
 
@@ -211,7 +211,7 @@ void
 InOrderThreadContext::setIntReg(int reg_idx, uint64_t val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenIntIndex(reg_idx);
     cpu->setIntReg(reg_idx, val, tid);
 }
 
@@ -219,7 +219,7 @@ void
 InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     cpu->setFloatReg(reg_idx, val, tid);
 }
 
@@ -227,7 +227,7 @@ void
 InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
     ThreadID tid = thread->threadId();
-    reg_idx = cpu->isa[tid].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[tid]->flattenFloatIndex(reg_idx);
     cpu->setFloatRegBits(reg_idx, val, tid);
 }
 
diff --git a/src/cpu/inorder/thread_context.hh b/src/cpu/inorder/thread_context.hh
index 2dd55582e..a959d71d6 100644
--- a/src/cpu/inorder/thread_context.hh
+++ b/src/cpu/inorder/thread_context.hh
@@ -254,10 +254,10 @@ class InOrderThreadContext : public ThreadContext
     void setMiscReg(int misc_reg, const MiscReg &val);
 
     int flattenIntIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenIntIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenIntIndex(reg); }
 
     int flattenFloatIndex(int reg)
-    { return cpu->isa[thread->threadId()].flattenFloatIndex(reg); }
+    { return cpu->isa[thread->threadId()]->flattenFloatIndex(reg); }
 
     void activateContext(Cycles delay)
     { cpu->activateContext(thread->threadId(), delay); }
diff --git a/src/cpu/o3/checker.cc b/src/cpu/o3/checker.cc
index c99428617..3ff3d86bc 100644
--- a/src/cpu/o3/checker.cc
+++ b/src/cpu/o3/checker.cc
@@ -82,6 +82,7 @@ O3CheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index c5421302d..9de1bf6b4 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -241,6 +241,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
                  TheISA::NumMiscRegs * numThreads,
                  TheISA::ZeroReg),
 
+      isa(numThreads, NULL),
+
       icachePort(&fetch, this),
       dcachePort(&iew.ldstQueue, this),
 
@@ -340,6 +342,8 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
     for (ThreadID tid = 0; tid < numThreads; tid++) {
         bool bindRegs = (tid <= active_threads - 1);
 
+        isa[tid] = params->isa[tid];
+
         commitRenameMap[tid].init(TheISA::NumIntRegs,
                                   params->numPhysIntRegs,
                                   lreg_idx,            //Index for Logical. Regs
@@ -1285,7 +1289,7 @@ template <class Impl>
 TheISA::MiscReg
 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
 {
-    return this->isa[tid].readMiscRegNoEffect(misc_reg);
+    return this->isa[tid]->readMiscRegNoEffect(misc_reg);
 }
 
 template <class Impl>
@@ -1293,7 +1297,7 @@ TheISA::MiscReg
 FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
 {
     miscRegfileReads++;
-    return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
+    return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
 }
 
 template <class Impl>
@@ -1301,7 +1305,7 @@ void
 FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
-    this->isa[tid].setMiscRegNoEffect(misc_reg, val);
+    this->isa[tid]->setMiscRegNoEffect(misc_reg, val);
 }
 
 template <class Impl>
@@ -1310,7 +1314,7 @@ FullO3CPU<Impl>::setMiscReg(int misc_reg,
         const TheISA::MiscReg &val, ThreadID tid)
 {
     miscRegfileWrites++;
-    this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
+    this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
 }
 
 template <class Impl>
diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh
index 1f9a8da6c..06e1ea336 100644
--- a/src/cpu/o3/cpu.hh
+++ b/src/cpu/o3/cpu.hh
@@ -634,7 +634,7 @@ class FullO3CPU : public BaseO3CPU
     /** Integer Register Scoreboard */
     Scoreboard scoreboard;
 
-    TheISA::ISA isa[Impl::MaxThreads];
+    std::vector<TheISA::ISA *> isa;
 
     /** Instruction port. Note that it has to appear after the fetch stage. */
     IcachePort icachePort;
diff --git a/src/cpu/o3/thread_context_impl.hh b/src/cpu/o3/thread_context_impl.hh
index 38e7c5dec..9d60a9700 100755
--- a/src/cpu/o3/thread_context_impl.hh
+++ b/src/cpu/o3/thread_context_impl.hh
@@ -219,14 +219,14 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::clearArchRegs()
 {
-    cpu->isa[thread->threadId()].clear();
+    cpu->isa[thread->threadId()]->clear();
 }
 
 template <class Impl>
 uint64_t
 O3ThreadContext<Impl>::readIntReg(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
     return cpu->readArchIntReg(reg_idx, thread->threadId());
 }
 
@@ -234,7 +234,7 @@ template <class Impl>
 TheISA::FloatReg
 O3ThreadContext<Impl>::readFloatReg(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     return cpu->readArchFloatReg(reg_idx, thread->threadId());
 }
 
@@ -242,7 +242,7 @@ template <class Impl>
 TheISA::FloatRegBits
 O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
 }
 
@@ -250,7 +250,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenIntIndex(reg_idx);
     cpu->setArchIntReg(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -260,7 +260,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     cpu->setArchFloatReg(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -270,7 +270,7 @@ template <class Impl>
 void
 O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
 {
-    reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
+    reg_idx = cpu->isa[thread->threadId()]->flattenFloatIndex(reg_idx);
     cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
 
     conditionalSquash();
@@ -298,14 +298,14 @@ template <class Impl>
 int
 O3ThreadContext<Impl>::flattenIntIndex(int reg)
 {
-    return cpu->isa[thread->threadId()].flattenIntIndex(reg);
+    return cpu->isa[thread->threadId()]->flattenIntIndex(reg);
 }
 
 template <class Impl>
 int
 O3ThreadContext<Impl>::flattenFloatIndex(int reg)
 {
-    return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
+    return cpu->isa[thread->threadId()]->flattenFloatIndex(reg);
 }
 
 template <class Impl>
diff --git a/src/cpu/ozone/checker_builder.cc b/src/cpu/ozone/checker_builder.cc
index f4bb03dcc..970591d33 100644
--- a/src/cpu/ozone/checker_builder.cc
+++ b/src/cpu/ozone/checker_builder.cc
@@ -89,6 +89,7 @@ OzoneCheckerParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
     params->system = system;
     params->cpu_id = cpu_id;
     params->profile = profile;
diff --git a/src/cpu/ozone/cpu_builder.cc b/src/cpu/ozone/cpu_builder.cc
index 65f68152f..ffd05375b 100644
--- a/src/cpu/ozone/cpu_builder.cc
+++ b/src/cpu/ozone/cpu_builder.cc
@@ -80,6 +80,7 @@ DerivOzoneCPUParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
 
     params->system = system;
     params->cpu_id = cpu_id;
diff --git a/src/cpu/ozone/simple_cpu_builder.cc b/src/cpu/ozone/simple_cpu_builder.cc
index 512dc3b9e..1fd9d3b79 100644
--- a/src/cpu/ozone/simple_cpu_builder.cc
+++ b/src/cpu/ozone/simple_cpu_builder.cc
@@ -83,6 +83,7 @@ SimpleOzoneCPUParams::create()
 
     params->itb = itb;
     params->dtb = dtb;
+    params->isa = isa;
 
     params->system = system;
     params->cpu_id = cpu_id;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 9ca943900..da965450a 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -87,10 +87,11 @@ BaseSimpleCPU::BaseSimpleCPU(BaseSimpleCPUParams *p)
     : BaseCPU(p), traceData(NULL), thread(NULL)
 {
     if (FullSystem)
-        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb);
+        thread = new SimpleThread(this, 0, p->system, p->itb, p->dtb,
+                                  p->isa[0]);
     else
         thread = new SimpleThread(this, /* thread_num */ 0, p->system,
-                p->workload[0], p->itb, p->dtb);
+                                  p->workload[0], p->itb, p->dtb, p->isa[0]);
 
     thread->setStatus(ThreadContext::Halted);
 
diff --git a/src/cpu/simple_thread.cc b/src/cpu/simple_thread.cc
index cf9bb4840..af121e43f 100644
--- a/src/cpu/simple_thread.cc
+++ b/src/cpu/simple_thread.cc
@@ -61,9 +61,9 @@ using namespace std;
 // constructor
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            Process *_process, TheISA::TLB *_itb,
-                           TheISA::TLB *_dtb)
-    : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb),
-      dtb(_dtb)
+                           TheISA::TLB *_dtb, TheISA::ISA *_isa)
+    : ThreadState(_cpu, _thread_num, _process), isa(_isa), system(_sys),
+      itb(_itb), dtb(_dtb)
 {
     clearArchRegs();
     tc = new ProxyThreadContext<SimpleThread>(this);
@@ -71,8 +71,9 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 
 SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
                            TheISA::TLB *_itb, TheISA::TLB *_dtb,
-                           bool use_kernel_stats)
-    : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb)
+                           TheISA::ISA *_isa, bool use_kernel_stats)
+    : ThreadState(_cpu, _thread_num, NULL), isa(_isa), system(_sys), itb(_itb),
+      dtb(_dtb)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 
@@ -99,7 +100,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys,
 }
 
 SimpleThread::SimpleThread()
-    : ThreadState(NULL, -1, NULL)
+    : ThreadState(NULL, -1, NULL), isa(NULL)
 {
     tc = new ProxyThreadContext<SimpleThread>(this);
 }
@@ -182,7 +183,7 @@ SimpleThread::serialize(ostream &os)
     // 
     // Now must serialize all the ISA dependent state
     //
-    isa.serialize(baseCpu, os);
+    isa->serialize(baseCpu, os);
 }
 
 
@@ -198,7 +199,7 @@ SimpleThread::unserialize(Checkpoint *cp, const std::string &section)
     // 
     // Now must unserialize all the ISA dependent state
     //
-    isa.unserialize(baseCpu, cp, section);
+    isa->unserialize(baseCpu, cp, section);
 }
 
 void
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 8594e4471..8e6df9466 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -108,7 +108,7 @@ class SimpleThread : public ThreadState
         FloatRegBits i[TheISA::NumFloatRegs];
     } floatRegs;
     TheISA::IntReg intRegs[TheISA::NumIntRegs];
-    TheISA::ISA isa;    // one "instance" of the current ISA.
+    TheISA::ISA *const isa;    // one "instance" of the current ISA.
 
     TheISA::PCState _pcState;
 
@@ -133,11 +133,12 @@ class SimpleThread : public ThreadState
     // constructor: initialize SimpleThread from given process structure
     // FS
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
-                 TheISA::TLB *_itb, TheISA::TLB *_dtb,
+                 TheISA::TLB *_itb, TheISA::TLB *_dtb, TheISA::ISA *_isa,
                  bool use_kernel_stats = true);
     // SE
     SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
-                 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb);
+                 Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb,
+                 TheISA::ISA *_isa);
 
     SimpleThread();
 
@@ -226,7 +227,7 @@ class SimpleThread : public ThreadState
         _pcState = 0;
         memset(intRegs, 0, sizeof(intRegs));
         memset(floatRegs.i, 0, sizeof(floatRegs.i));
-        isa.clear();
+        isa->clear();
     }
 
     //
@@ -234,7 +235,7 @@ class SimpleThread : public ThreadState
     //
     uint64_t readIntReg(int reg_idx)
     {
-        int flatIndex = isa.flattenIntIndex(reg_idx);
+        int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
         uint64_t regVal = intRegs[flatIndex];
         DPRINTF(IntRegs, "Reading int reg %d (%d) as %#x.\n",
@@ -244,7 +245,7 @@ class SimpleThread : public ThreadState
 
     FloatReg readFloatReg(int reg_idx)
     {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
+        int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
         FloatReg regVal = floatRegs.f[flatIndex];
         DPRINTF(FloatRegs, "Reading float reg %d (%d) as %f, %#x.\n",
@@ -254,7 +255,7 @@ class SimpleThread : public ThreadState
 
     FloatRegBits readFloatRegBits(int reg_idx)
     {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
+        int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
         FloatRegBits regVal = floatRegs.i[flatIndex];
         DPRINTF(FloatRegs, "Reading float reg %d (%d) bits as %#x, %f.\n",
@@ -264,7 +265,7 @@ class SimpleThread : public ThreadState
 
     void setIntReg(int reg_idx, uint64_t val)
     {
-        int flatIndex = isa.flattenIntIndex(reg_idx);
+        int flatIndex = isa->flattenIntIndex(reg_idx);
         assert(flatIndex < TheISA::NumIntRegs);
         DPRINTF(IntRegs, "Setting int reg %d (%d) to %#x.\n",
                 reg_idx, flatIndex, val);
@@ -273,7 +274,7 @@ class SimpleThread : public ThreadState
 
     void setFloatReg(int reg_idx, FloatReg val)
     {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
+        int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
         floatRegs.f[flatIndex] = val;
         DPRINTF(FloatRegs, "Setting float reg %d (%d) to %f, %#x.\n",
@@ -282,7 +283,7 @@ class SimpleThread : public ThreadState
 
     void setFloatRegBits(int reg_idx, FloatRegBits val)
     {
-        int flatIndex = isa.flattenFloatIndex(reg_idx);
+        int flatIndex = isa->flattenFloatIndex(reg_idx);
         assert(flatIndex < TheISA::NumFloatRegs);
         // XXX: Fix array out of bounds compiler error for gem5.fast
         // when checkercpu enabled
@@ -341,37 +342,37 @@ class SimpleThread : public ThreadState
     MiscReg
     readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
     {
-        return isa.readMiscRegNoEffect(misc_reg);
+        return isa->readMiscRegNoEffect(misc_reg);
     }
 
     MiscReg
     readMiscReg(int misc_reg, ThreadID tid = 0)
     {
-        return isa.readMiscReg(misc_reg, tc);
+        return isa->readMiscReg(misc_reg, tc);
     }
 
     void
     setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return isa.setMiscRegNoEffect(misc_reg, val);
+        return isa->setMiscRegNoEffect(misc_reg, val);
     }
 
     void
     setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
     {
-        return isa.setMiscReg(misc_reg, val, tc);
+        return isa->setMiscReg(misc_reg, val, tc);
     }
 
     int
     flattenIntIndex(int reg)
     {
-        return isa.flattenIntIndex(reg);
+        return isa->flattenIntIndex(reg);
     }
 
     int
     flattenFloatIndex(int reg)
     {
-        return isa.flattenFloatIndex(reg);
+        return isa->flattenFloatIndex(reg);
     }
 
     unsigned readStCondFailures() { return storeCondFailures; }
diff --git a/tests/run.py b/tests/run.py
index d0239b2b1..1671d1714 100644
--- a/tests/run.py
+++ b/tests/run.py
@@ -77,6 +77,31 @@ maxtick = m5.MaxTick
 sys.path.append(joinpath(tests_root, category, mode, name))
 execfile(joinpath(tests_root, category, mode, name, 'test.py'))
 
+# Initialize all CPUs in a system
+def initCPUs(sys):
+    def initCPU(cpu):
+        # We might actually have a MemTest object or something similar
+        # here that just pretends to be a CPU.
+        if isinstance(cpu, BaseCPU):
+            cpu.createThreads()
+
+    # The CPU attribute doesn't exist in some cases, e.g. the Ruby
+    # testers.
+    if not hasattr(sys, "cpu"):
+        return
+
+    # The CPU can either be a list of CPUs or a single object.
+    if isinstance(sys.cpu, list):
+        [ initCPU(cpu) for cpu in sys.cpu ]
+    else:
+        initCPU(sys.cpu)
+
+# We might be creating a single system or a dual system. Try
+# initializing the CPUs in all known system attributes.
+for sysattr in [ "system", "testsys", "drivesys" ]:
+    if hasattr(root, sysattr):
+        initCPUs(getattr(root, sysattr))
+
 # instantiate configuration
 m5.instantiate()