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ARM: Fix multiply overflow flag setting.

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Gabe Black 2010-06-02 12:58:06 -05:00
parent 90c2284714
commit 3cff58602a
1 changed files with 12 additions and 0 deletions
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12
src/arch/arm/isa/insts/mult.isa
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@ -165,6 +165,8 @@ let {{
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
Reg3.sw; Reg3.sw;
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smladx", '''Reg0 = resTemp = buildMult4InstCc ("smladx", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
@ -172,6 +174,8 @@ let {{
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
Reg3.sw; Reg3.sw;
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) + buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
(int64_t)((Reg1.ud << 32) | Reg0.ud); (int64_t)((Reg1.ud << 32) | Reg0.ud);
@ -246,6 +250,8 @@ let {{
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
Reg3.sw; Reg3.sw;
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstCc ("smlsdx", '''Reg0 = resTemp = buildMult4InstCc ("smlsdx", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
@ -253,6 +259,8 @@ let {{
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
Reg3.sw; Reg3.sw;
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult4InstUnCc("smlsld", '''resTemp = buildMult4InstUnCc("smlsld", '''resTemp =
sext<16>(bits(Reg2, 15, 0)) * sext<16>(bits(Reg2, 15, 0)) *
@ -306,12 +314,16 @@ let {{
sext<16>(bits(Reg2, 15, 0)) + sext<16>(bits(Reg2, 15, 0)) +
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 31, 16)); sext<16>(bits(Reg2, 31, 16));
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult3InstCc ("smuadx", '''Reg0 = resTemp = buildMult3InstCc ("smuadx", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *
sext<16>(bits(Reg2, 31, 16)) + sext<16>(bits(Reg2, 31, 16)) +
sext<16>(bits(Reg1, 31, 16)) * sext<16>(bits(Reg1, 31, 16)) *
sext<16>(bits(Reg2, 15, 0)); sext<16>(bits(Reg2, 15, 0));
resTemp = bits(resTemp, 32) !=
bits(resTemp, 31);
''', "overflow") ''', "overflow")
buildMult3InstUnCc("smulbb", '''Reg0 = resTemp = buildMult3InstUnCc("smulbb", '''Reg0 = resTemp =
sext<16>(bits(Reg1, 15, 0)) * sext<16>(bits(Reg1, 15, 0)) *