From 3cd349f44305d6ca9496f7f626f0f4f939bd84ad Mon Sep 17 00:00:00 2001
From: Gabe Black <gblack@eecs.umich.edu>
Date: Tue, 23 Nov 2010 06:10:17 -0500
Subject: [PATCH] X86: Obey the PCD (cache disable) bit in the page tables.

---
 src/arch/x86/tlb.cc | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/arch/x86/tlb.cc b/src/arch/x86/tlb.cc
index 4c8d96f8b..52d9cdf9c 100644
--- a/src/arch/x86/tlb.cc
+++ b/src/arch/x86/tlb.cc
@@ -653,6 +653,8 @@ TLB::translate(RequestPtr req, ThreadContext *tc, Translation *translation,
             Addr paddr = entry->paddr | (vaddr & (entry->size-1));
             DPRINTF(TLB, "Translated %#x -> %#x.\n", vaddr, paddr);
             req->setPaddr(paddr);
+            if (entry->uncacheable)
+                req->setFlags(Request::UNCACHEABLE);
         } else {
             //Use the address which already has segmentation applied.
             DPRINTF(TLB, "Paging disabled.\n");