ruby: move functional access to ruby system
This patch moves the code for functional accesses to ruby system. This is because the subsequent patches add support for making functional accesses to the messages in the interconnect. Making those accesses from the ruby port would be cumbersome.
This commit is contained in:
Nilay Vaish
parent
95664da097
commit
3c9d3b16d8
4 changed files with 180 additions and 188 deletions
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@ -234,189 +234,6 @@ RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
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return false;
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}
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bool
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RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
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{
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Address address(pkt->getAddr());
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Address line_address(address);
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line_address.makeLineAddress();
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = ruby_system->m_abs_cntrl_vec.size();
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DPRINTF(RubyPort, "Functional Read request for %s\n",address);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_address);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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assert(num_rw <= 1);
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uint8_t *data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = address.getAddress() - line_address.getAddress();
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// This if case is meant to capture what happens in a Broadcast/Snoop
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// protocol where the block does not exist in the cache hierarchy. You
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// only want to read from the Backing_Store memory if there is no copy in
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// the cache hierarchy, otherwise you want to try to read the RO or RW
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// copies existing in the cache hierarchy (covered by the else statement).
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// The reason is because the Backing_Store memory could easily be stale, if
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// there are copies floating around the cache hierarchy, so you want to read
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// it only if it's not in the cache hierarchy at all.
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if (num_invalid == (num_controllers - 1) &&
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num_backing_store == 1)
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{
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DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n");
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]
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->getAccessPermission(line_address);
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if (access_perm == AccessPermission_Backing_Store) {
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_address);
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DPRINTF(RubyPort, "reading from %s block %s\n",
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ruby_system->m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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} else {
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// In Broadcast/Snoop protocols, this covers if you know the block
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// exists somewhere in the caching hierarchy, then you want to read any
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// valid RO or RW block. In directory protocols, same thing, you want
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// to read any valid readable copy of the block.
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DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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// In this loop, we try to figure which controller has a read only or
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// a read write copy of the given address. Any valid copy would suffice
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// for a functional read.
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for(int i = 0;i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]
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->getAccessPermission(line_address);
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if(access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write)
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{
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_address);
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DPRINTF(RubyPort, "reading from %s block %s\n",
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ruby_system->m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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}
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return false;
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}
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bool
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RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
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{
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Address addr(pkt->getAddr());
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Address line_addr = line_address(addr);
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = ruby_system->m_abs_cntrl_vec.size();
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DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for(int i = 0;i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_addr);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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// If the number of read write copies is more than 1, then there is bug in
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// coherence protocol. Otherwise, if all copies are in stable states, i.e.
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// num_busy == 0, we update all the copies. If there is at least one copy
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// in busy state, then we check if there is read write copy. If yes, then
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// also we let the access go through. Or, if there is no copy in the cache
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// hierarchy at all, we still want to do the write to the memory
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// (Backing_Store) instead of failing.
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DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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assert(num_rw <= 1);
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uint8_t *data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = addr.getAddress() - line_addr.getAddress();
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if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
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(num_invalid == (num_controllers - 1) && num_backing_store == 1))
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{
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for(int i = 0; i < num_controllers;++i) {
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access_perm = ruby_system->m_abs_cntrl_vec[i]->
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getAccessPermission(line_addr);
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if(access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write||
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access_perm == AccessPermission_Maybe_Stale ||
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access_perm == AccessPermission_Backing_Store)
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{
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DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
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->getDataBlock(line_addr);
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DPRINTF(RubyPort, "%s\n",block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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block.setByte(i + startByte, data[i]);
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}
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DPRINTF(RubyPort, "%s\n",block);
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}
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}
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return true;
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}
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return false;
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}
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void
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RubyPort::M5Port::recvFunctional(PacketPtr pkt)
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{
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@ -441,9 +258,9 @@ RubyPort::M5Port::recvFunctional(PacketPtr pkt)
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// Do the functional access on ruby memory
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if (pkt->isRead()) {
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accessSucceeded = doFunctionalRead(pkt);
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accessSucceeded = ruby_system->functionalRead(pkt);
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} else if (pkt->isWrite()) {
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accessSucceeded = doFunctionalWrite(pkt);
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accessSucceeded = ruby_system->functionalWrite(pkt);
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} else {
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panic("RubyPort: unsupported functional command %s\n",
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pkt->cmdString());
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@ -89,8 +89,6 @@ class RubyPort : public MemObject
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private:
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bool isPhysMemAddress(Addr addr);
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bool doFunctionalRead(PacketPtr pkt);
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bool doFunctionalWrite(PacketPtr pkt);
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};
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friend class M5Port;
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@ -34,6 +34,7 @@
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#include "base/intmath.hh"
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#include "base/output.hh"
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#include "debug/RubyCacheTrace.hh"
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#include "debug/RubySystem.hh"
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#include "mem/ruby/common/Address.hh"
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#include "mem/ruby/network/Network.hh"
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#include "mem/ruby/profiler/Profiler.hh"
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@ -396,6 +397,179 @@ RubySystem::clearStats() const
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m_network_ptr->clearStats();
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}
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bool
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RubySystem::functionalRead(PacketPtr pkt)
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{
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Address address(pkt->getAddr());
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Address line_address(address);
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line_address.makeLineAddress();
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = m_abs_cntrl_vec.size();
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DPRINTF(RubySystem, "Functional Read request for %s\n",address);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = m_abs_cntrl_vec[i]-> getAccessPermission(line_address);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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assert(num_rw <= 1);
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uint8_t *data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = address.getAddress() - line_address.getAddress();
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// This if case is meant to capture what happens in a Broadcast/Snoop
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// protocol where the block does not exist in the cache hierarchy. You
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// only want to read from the Backing_Store memory if there is no copy in
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// the cache hierarchy, otherwise you want to try to read the RO or RW
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// copies existing in the cache hierarchy (covered by the else statement).
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// The reason is because the Backing_Store memory could easily be stale, if
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// there are copies floating around the cache hierarchy, so you want to read
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// it only if it's not in the cache hierarchy at all.
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if (num_invalid == (num_controllers - 1) &&
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num_backing_store == 1) {
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DPRINTF(RubySystem, "only copy in Backing_Store memory, read from it\n");
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for (int i = 0; i < num_controllers; ++i) {
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access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_address);
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if (access_perm == AccessPermission_Backing_Store) {
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DataBlock& block = m_abs_cntrl_vec[i]->
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getDataBlock(line_address);
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DPRINTF(RubySystem, "reading from %s block %s\n",
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m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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} else {
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// In Broadcast/Snoop protocols, this covers if you know the block
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// exists somewhere in the caching hierarchy, then you want to read any
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// valid RO or RW block. In directory protocols, same thing, you want
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// to read any valid readable copy of the block.
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DPRINTF(RubySystem, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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// In this loop, we try to figure which controller has a read only or
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// a read write copy of the given address. Any valid copy would suffice
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// for a functional read.
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for (int i = 0;i < num_controllers;++i) {
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access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_address);
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if (access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write) {
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DataBlock& block = m_abs_cntrl_vec[i]->
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getDataBlock(line_address);
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DPRINTF(RubySystem, "reading from %s block %s\n",
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m_abs_cntrl_vec[i]->name(), block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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data[i] = block.getByte(i + startByte);
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}
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return true;
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}
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}
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}
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return false;
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}
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bool
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RubySystem::functionalWrite(PacketPtr pkt)
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{
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Address addr(pkt->getAddr());
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Address line_addr = line_address(addr);
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AccessPermission access_perm = AccessPermission_NotPresent;
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int num_controllers = m_abs_cntrl_vec.size();
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DPRINTF(RubySystem, "Functional Write request for %s\n",addr);
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unsigned int num_ro = 0;
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unsigned int num_rw = 0;
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unsigned int num_busy = 0;
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unsigned int num_backing_store = 0;
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unsigned int num_invalid = 0;
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// In this loop we count the number of controllers that have the given
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// address in read only, read write and busy states.
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for (int i = 0;i < num_controllers;++i) {
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access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_addr);
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if (access_perm == AccessPermission_Read_Only)
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num_ro++;
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else if (access_perm == AccessPermission_Read_Write)
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num_rw++;
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else if (access_perm == AccessPermission_Busy)
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num_busy++;
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else if (access_perm == AccessPermission_Backing_Store)
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// See RubySlicc_Exports.sm for details, but Backing_Store is meant
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// to represent blocks in memory *for Broadcast/Snooping protocols*,
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// where memory has no idea whether it has an exclusive copy of data
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// or not.
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num_backing_store++;
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else if (access_perm == AccessPermission_Invalid ||
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access_perm == AccessPermission_NotPresent)
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num_invalid++;
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}
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// If the number of read write copies is more than 1, then there is bug in
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// coherence protocol. Otherwise, if all copies are in stable states, i.e.
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// num_busy == 0, we update all the copies. If there is at least one copy
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// in busy state, then we check if there is read write copy. If yes, then
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// also we let the access go through. Or, if there is no copy in the cache
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// hierarchy at all, we still want to do the write to the memory
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// (Backing_Store) instead of failing.
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DPRINTF(RubySystem, "num_busy = %d, num_ro = %d, num_rw = %d\n",
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num_busy, num_ro, num_rw);
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assert(num_rw <= 1);
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uint8_t *data = pkt->getPtr<uint8_t>(true);
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unsigned int size_in_bytes = pkt->getSize();
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unsigned startByte = addr.getAddress() - line_addr.getAddress();
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if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
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(num_invalid == (num_controllers - 1) && num_backing_store == 1)) {
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for (int i = 0; i < num_controllers;++i) {
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access_perm = m_abs_cntrl_vec[i]->getAccessPermission(line_addr);
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if (access_perm == AccessPermission_Read_Only ||
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access_perm == AccessPermission_Read_Write||
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access_perm == AccessPermission_Maybe_Stale ||
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access_perm == AccessPermission_Backing_Store) {
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DataBlock& block = m_abs_cntrl_vec[i]->getDataBlock(line_addr);
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DPRINTF(RubySystem, "%s\n",block);
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for (unsigned i = 0; i < size_in_bytes; ++i) {
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block.setByte(i + startByte, data[i]);
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}
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DPRINTF(RubySystem, "%s\n",block);
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}
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}
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return true;
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}
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return false;
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}
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#ifdef CHECK_COHERENCE
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// This code will check for cases if the given cache block is exclusive in
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// one node and shared in another-- a coherence violation
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@ -36,6 +36,7 @@
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#define __MEM_RUBY_SYSTEM_SYSTEM_HH__
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#include "base/callback.hh"
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#include "mem/packet.hh"
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#include "mem/ruby/common/Global.hh"
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#include "mem/ruby/recorder/CacheRecorder.hh"
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#include "mem/ruby/slicc_interface/AbstractController.hh"
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@ -112,6 +113,8 @@ class RubySystem : public ClockedObject
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void unserialize(Checkpoint *cp, const std::string §ion);
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void process();
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void startup();
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bool functionalRead(Packet *ptr);
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bool functionalWrite(Packet *ptr);
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void registerNetwork(Network*);
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void registerProfiler(Profiler*);
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|||
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Reference in a new issue