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ruby: cleaned up access permission enum

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This commit is contained in:
Brad Beckmann 2011-02-23 16:41:58 -08:00
parent c09a33e5d5
commit 3bc33eeaea
4 changed files with 16 additions and 11 deletions
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2
src/mem/protocol/MESI_CMP_directory-L2cache.sm
View file

@ -219,7 +219,7 @@ machine(L2Cache, "MESI Directory L2 Cache CMP")
} else if (state == State:M) { } else if (state == State:M) {
cache_entry.changePermission(AccessPermission:Read_Write); cache_entry.changePermission(AccessPermission:Read_Write);
} else if (state == State:MT) { } else if (state == State:MT) {
cache_entry.changePermission(AccessPermission:Stale); cache_entry.changePermission(AccessPermission:Invalid);
} else { } else {
cache_entry.changePermission(AccessPermission:Busy); cache_entry.changePermission(AccessPermission:Busy);
} }

20
src/mem/protocol/RubySlicc_Exports.sm
View file

@ -47,14 +47,20 @@ external_type(DataBlock, desc="..."){
// Declarations of external types that are common to all protocols // Declarations of external types that are common to all protocols
// AccessPermission // AccessPermission
// The following five states define the access permission of all memory blocks.
// These permissions have multiple uses. They coordinate locking and
// synchronization primitives, as well as enable functional accesses.
// One should not need to add any additional permission values and it is very
// risky to do so.
enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") { enumeration(AccessPermission, desc="...", default="AccessPermission_NotPresent") {
Busy, desc="No Read or Write"; // Valid data
Read_Only, desc="Read Only"; Read_Only, desc="block is Read Only (modulo functional writes)";
Read_Write, desc="Read/Write"; Read_Write, desc="block is Read/Write";
Invalid, desc="Invalid";
NotPresent, desc="NotPresent"; // Invalid data
ReadUpgradingToWrite, desc="Read only, but trying to get Read/Write"; Invalid, desc="block is in an Invalid base state";
Stale, desc="local L1 has a modified copy, assume L2 copy is stale data"; NotPresent, desc="block is NotPresent";
Busy, desc="block is in a transient state, currently invalid";
} }
// TesterStatus // TesterStatus

3
src/mem/ruby/slicc_interface/AbstractCacheEntry.cc
View file

@ -50,8 +50,7 @@ AbstractCacheEntry::changePermission(AccessPermission new_perm)
{ {
m_Permission = new_perm; m_Permission = new_perm;
if ((new_perm == AccessPermission_Invalid) || if ((new_perm == AccessPermission_Invalid) ||
(new_perm == AccessPermission_NotPresent) || (new_perm == AccessPermission_NotPresent)) {
(new_perm == AccessPermission_Stale)) {
m_locked = -1; m_locked = -1;
} }
} }

2
src/mem/ruby/system/PerfectCacheMemory.hh
View file

@ -149,7 +149,7 @@ inline void
PerfectCacheMemory<ENTRY>::allocate(const Address& address) PerfectCacheMemory<ENTRY>::allocate(const Address& address)
{ {
PerfectCacheLineState<ENTRY> line_state; PerfectCacheLineState<ENTRY> line_state;
line_state.m_permission = AccessPermission_Busy; line_state.m_permission = AccessPermission_Invalid;
line_state.m_entry = ENTRY(); line_state.m_entry = ENTRY();
m_map[line_address(address)] = line_state; m_map[line_address(address)] = line_state;
} }