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Get the "hard" SPARC instructions working in o3. I don't like that the IsStoreConditional flag needs to be set for them because they aren't store conditional instructions, and I should fix the format code which is not handling the opt_flags correctly.

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--HG--
extra : convert_revision : cfd32808592832d7b6fbdaace5ae7b17c8a246e9
This commit is contained in:
Gabe Black 2007-04-08 01:42:42 +00:00
parent 3c9768e644
commit 3bb5fd8c44
3 changed files with 13 additions and 7 deletions
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10
src/arch/sparc/isa/formats/mem/swap.isa
View file

@ -137,7 +137,7 @@ def format Swap(code, postacc_code, mem_flags, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, SwapFuncs, '', name, Name, flags, decode_block) = doMemFormat(code, SwapFuncs, '', name, Name, flags,
opt_flags, postacc_code) ["IsStoreConditional"], postacc_code)
}}; }};
def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
@ -148,7 +148,7 @@ def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doMemFormat(code, SwapFuncs, AlternateASIPrivFaultCheck, decode_block) = doMemFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
name, Name, flags, opt_flags, postacc_code) name, Name, flags, ["IsStoreConditional"], postacc_code)
}}; }};
@ -163,8 +163,8 @@ let {{
decode_block = BasicDecode.subst(iop) decode_block = BasicDecode.subst(iop)
microParams = {"code": code, "postacc_code" : postacc_code, microParams = {"code": code, "postacc_code" : postacc_code,
"ea_code" : addrCalcReg, "fault_check" : faultCode} "ea_code" : addrCalcReg, "fault_check" : faultCode}
exec_output = doSplitExecute(execute, name, Name, asi, opt_flags, exec_output = doSplitExecute(execute, name, Name, asi,
microParams); ["IsStoreConditional"], microParams);
return (header_output, decoder_output, exec_output, decode_block) return (header_output, decoder_output, exec_output, decode_block)
}}; }};
@ -177,7 +177,7 @@ def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
decoder_output, decoder_output,
exec_output, exec_output,
decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck, decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
name, Name, flags, opt_flags, postacc_code) name, Name, flags, ["IsStoreConditional"], postacc_code)
}}; }};

5
src/cpu/base_dyn_inst.hh
View file

@ -877,6 +877,11 @@ BaseDynInst<Impl>::write(T data, Addr addr, unsigned flags, uint64_t *res)
effAddrValid = true; effAddrValid = true;
physEffAddr = req->getPaddr(); physEffAddr = req->getPaddr();
memReqFlags = req->getFlags(); memReqFlags = req->getFlags();
if (req->isCondSwap()) {
assert(res);
req->setExtraData(*res);
}
#if 0 #if 0
if (cpu->system->memctrl->badaddr(physEffAddr)) { if (cpu->system->memctrl->badaddr(physEffAddr)) {
fault = TheISA::genMachineCheckFault(); fault = TheISA::genMachineCheckFault();

5
src/cpu/o3/lsq_unit_impl.hh
View file

@ -647,7 +647,8 @@ LSQUnit<Impl>::writebackStores()
memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize()); memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
PacketPtr data_pkt = new Packet(req, MemCmd::WriteReq, MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
PacketPtr data_pkt = new Packet(req, command,
Packet::Broadcast); Packet::Broadcast);
data_pkt->dataStatic(inst->memData); data_pkt->dataStatic(inst->memData);
@ -664,7 +665,7 @@ LSQUnit<Impl>::writebackStores()
inst->seqNum); inst->seqNum);
// @todo: Remove this SC hack once the memory system handles it. // @todo: Remove this SC hack once the memory system handles it.
if (req->isLocked()) { if (inst->isStoreConditional()) {
// Disable recording the result temporarily. Writing to // Disable recording the result temporarily. Writing to
// misc regs normally updates the result, but this is not // misc regs normally updates the result, but this is not
// the desired behavior when handling store conditionals. // the desired behavior when handling store conditionals.