diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 1198f852f..9e760fbdf 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -1386,7 +1386,7 @@ ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
                 oc = sys->getThreadContext(x);
                 assert(oc->getITBPtr() && oc->getDTBPtr());
                 asid = bits(newVal, 63, 48);
-                if (haveLargeAsid64)
+                if (!haveLargeAsid64)
                     asid &= mask(8);
                 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
                 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
@@ -1941,10 +1941,10 @@ ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc)
 }
 
 void
-ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
-            uint8_t target_el)
+ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
+            bool secure_lookup, uint8_t target_el)
 {
-    if (haveLargeAsid64)
+    if (!haveLargeAsid64)
         asid &= mask(8);
     Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
     System *sys = tc->getSystemPtr();
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index ae5ff2131..df1b49a99 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -221,7 +221,7 @@ namespace ArmISA
             assert(!cpsr.width);
         }
 
-        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid,
+        void tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid,
                     bool secure_lookup, uint8_t target_el);
 
         void tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el);