merge from head
--HG-- extra : convert_revision : 21f7afe2719c00744c0981212c1ee6e442238e01
This commit is contained in:
commit
3afc625975
23 changed files with 252 additions and 140 deletions
|
@ -134,6 +134,9 @@ if len(bm) == 2:
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.connectMemPorts(drive_sys.membus)
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if options.kernel is not None:
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drive_sys.kernel = binary(options.kernel)
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root = makeDualRoot(test_sys, drive_sys, options.etherdump)
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elif len(bm) == 1:
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root = Root(system=test_sys)
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|
|
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@ -64,7 +64,7 @@ if args:
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process = LiveProcess()
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process.executable = options.cmd
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process.cmd = options.cmd + " " + options.options
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process.cmd = [options.cmd] + options.options.split()
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if options.input != "":
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process.input = options.input
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|
|
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@ -57,7 +57,7 @@ class ThreadInfo
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* thread_info struct. So we can get the address by masking off
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* the lower 14 bits.
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*/
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current = tc->readIntReg(TheISA::StackPointerReg) & ~0x3fff;
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current = tc->readIntReg(TheISA::StackPointerReg) & ~ULL(0x3fff);
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return VPtr<thread_info>(tc, current);
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}
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|
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@ -73,7 +73,7 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
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if (machInst.sib.base == INTREG_RBP && machInst.modRM.mod == 0)
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base = NUM_INTREGS;
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//In -this- special case, we don't use an index.
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if (machInst.sib.index == INTREG_RSP)
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if (index == INTREG_RSP)
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index = NUM_INTREGS;
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} else {
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if (machInst.addrSize == 2) {
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@ -82,11 +82,9 @@ void EmulEnv::doModRM(const ExtMachInst & machInst)
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scale = 0;
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base = machInst.modRM.rm | (machInst.rex.b << 3);
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if (machInst.modRM.mod == 0 && machInst.modRM.rm == 5) {
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base = NUM_INTREGS;
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//Since we need to use a different encoding of this
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//instruction anyway, just ignore the base in those cases
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// if (machInst.mode.submode == SixtyFourBitMode)
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// base = NUM_INTREGS+7;
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base = NUM_INTREGS;
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}
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}
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}
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|
|
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@ -167,7 +167,7 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
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filename = argv[0];
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//We want 16 byte alignment
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Addr alignmentMask = ~mask(4);
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uint64_t align = 16;
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// load object file into target memory
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objFile->loadSections(initVirtMem);
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@ -285,47 +285,35 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
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//Figure out how big the initial stack needs to be
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// The unaccounted for 0 at the top of the stack
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int mysterious_size = intSize;
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// A sentry NULL void pointer at the top of the stack.
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int sentry_size = intSize;
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//This is the name of the file which is present on the initial stack
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//It's purpose is to let the user space linker examine the original file.
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int file_name_size = filename.size();
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int file_name_size = filename.size() + 1;
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string platform = "x86_64";
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int aux_data_size = platform.size() + 1;
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int env_data_size = 0;
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for (int i = 0; i < envp.size(); ++i) {
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env_data_size += envp[i].size();
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env_data_size += envp[i].size() + 1;
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}
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int arg_data_size = 0;
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for (int i = 0; i < argv.size(); ++i) {
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arg_data_size += argv[i].size();
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arg_data_size += argv[i].size() + 1;
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}
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//The auxiliary vector data needs to be padded so it's size is a multiple
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//of the alignment mask.
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int aux_padding =
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((aux_data_size + ~alignmentMask) & alignmentMask) - aux_data_size;
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//The info_block needs to be padded so it's size is a multiple of the
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//alignment mask. Also, it appears that there needs to be at least some
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//padding, so if the size is already a multiple, we need to increase it
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//anyway.
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int info_block_size =
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(mysterious_size +
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file_name_size +
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env_data_size +
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arg_data_size +
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~alignmentMask) & alignmentMask;
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int base_info_block_size =
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sentry_size + file_name_size + env_data_size + arg_data_size;
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int info_block_padding =
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info_block_size -
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mysterious_size -
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file_name_size -
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env_data_size -
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arg_data_size;
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int info_block_size = roundUp(base_info_block_size, align);
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int info_block_padding = info_block_size - base_info_block_size;
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//Each auxilliary vector is two 8 byte words
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int aux_array_size = intSize * 2 * (auxv.size() + 1);
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|
@ -335,17 +323,27 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
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int argc_size = intSize;
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int space_needed =
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info_block_size +
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aux_data_size +
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aux_padding +
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//Figure out the size of the contents of the actual initial frame
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int frame_size =
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aux_array_size +
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envp_array_size +
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argv_array_size +
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argc_size;
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|
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//There needs to be padding after the auxiliary vector data so that the
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//very bottom of the stack is aligned properly.
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int partial_size = frame_size + aux_data_size;
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int aligned_partial_size = roundUp(partial_size, align);
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int aux_padding = aligned_partial_size - partial_size;
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int space_needed =
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info_block_size +
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aux_data_size +
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aux_padding +
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frame_size;
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stack_min = stack_base - space_needed;
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stack_min &= alignmentMask;
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stack_min = roundDown(stack_min, align);
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stack_size = stack_base - stack_min;
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|
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// map memory
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|
@ -353,11 +351,11 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
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roundUp(stack_size, pageSize));
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// map out initial stack contents
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Addr mysterious_base = stack_base - mysterious_size;
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Addr file_name_base = mysterious_base - file_name_size;
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Addr sentry_base = stack_base - sentry_size;
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Addr file_name_base = sentry_base - file_name_size;
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Addr env_data_base = file_name_base - env_data_size;
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Addr arg_data_base = env_data_base - arg_data_size;
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Addr aux_data_base = arg_data_base - aux_data_size - info_block_padding;
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Addr aux_data_base = arg_data_base - info_block_padding - aux_data_size;
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Addr auxv_array_base = aux_data_base - aux_array_size - aux_padding;
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Addr envp_array_base = auxv_array_base - envp_array_size;
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Addr argv_array_base = envp_array_base - argv_array_size;
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|
@ -380,10 +378,10 @@ X86LiveProcess::argsInit(int intSize, int pageSize)
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uint64_t argc = argv.size();
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uint64_t guestArgc = TheISA::htog(argc);
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//Write out the mysterious 0
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uint64_t mysterious_zero = 0;
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initVirtMem->writeBlob(mysterious_base,
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(uint8_t*)&mysterious_zero, mysterious_size);
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//Write out the sentry void *
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uint64_t sentry_NULL = 0;
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initVirtMem->writeBlob(sentry_base,
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(uint8_t*)&sentry_NULL, sentry_size);
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//Write the file name
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initVirtMem->writeString(file_name_base, filename.c_str());
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|
|
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@ -87,7 +87,7 @@ OutputDirectory::resolve(const string &name)
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}
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||||
|
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ostream *
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OutputDirectory::create(const string &name)
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OutputDirectory::create(const string &name, bool binary)
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{
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if (name == "cerr" || name == "stderr")
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return &cerr;
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@ -95,7 +95,8 @@ OutputDirectory::create(const string &name)
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if (name == "cout" || name == "stdout")
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return &cout;
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ofstream *file = new ofstream(resolve(name).c_str(), ios::trunc);
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ofstream *file = new ofstream(resolve(name).c_str(),
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ios::trunc | binary ? ios::binary : (ios::openmode)0);
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if (!file->is_open())
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panic("Cannot open file %s", name);
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|
|
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@ -51,7 +51,7 @@ class OutputDirectory
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const std::string &directory();
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std::string resolve(const std::string &name);
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std::ostream *create(const std::string &name);
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std::ostream *create(const std::string &name, bool binary = false);
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std::ostream *find(const std::string &name);
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static bool isFile(const std::ostream *os);
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||||
|
|
|
@ -53,7 +53,6 @@ SwigSource('m5.internal', 'swig/core.i')
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SwigSource('m5.internal', 'swig/debug.i')
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SwigSource('m5.internal', 'swig/event.i')
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SwigSource('m5.internal', 'swig/random.i')
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SwigSource('m5.internal', 'swig/sim_object.i')
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SwigSource('m5.internal', 'swig/stats.i')
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SwigSource('m5.internal', 'swig/trace.i')
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PySource('m5.internal', 'm5/internal/__init__.py')
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|
|
|
@ -274,17 +274,29 @@ class Generate(object):
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print >>out
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||||
|
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for obj in ordered_objs:
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code = 'class %s ' % obj.cxx_class
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if str(obj) != 'SimObject':
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code += ': public %s ' % obj.__bases__[0]
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code += '{};'
|
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if obj.swig_objdecls:
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for decl in obj.swig_objdecls:
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print >>out, decl
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continue
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||||
code = ''
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||||
base = obj.get_base()
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||||
|
||||
code += '// stop swig from creating/wrapping default ctor/dtor\n'
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||||
code += '%%nodefault %s;\n' % obj.cxx_class
|
||||
code += 'class %s ' % obj.cxx_class
|
||||
if base:
|
||||
code += ': public %s' % base
|
||||
code += ' {};\n'
|
||||
|
||||
klass = obj.cxx_class;
|
||||
if hasattr(obj, 'cxx_namespace'):
|
||||
code = 'namespace %s { %s }' % (obj.cxx_namespace, code)
|
||||
new_code = 'namespace %s {\n' % obj.cxx_namespace
|
||||
new_code += code
|
||||
new_code += '}\n'
|
||||
code = new_code
|
||||
klass = '%s::%s' % (obj.cxx_namespace, klass)
|
||||
|
||||
print >>out, '%%ignore %s;' % klass
|
||||
print >>out, code
|
||||
|
||||
for obj in ordered_objs:
|
||||
|
|
|
@ -128,6 +128,7 @@ class MetaSimObject(type):
|
|||
'cxx_class' : types.StringType,
|
||||
'cxx_type' : types.StringType,
|
||||
'cxx_predecls' : types.ListType,
|
||||
'swig_objdecls' : types.ListType,
|
||||
'swig_predecls' : types.ListType,
|
||||
'type' : types.StringType }
|
||||
# Attributes that can be set any time
|
||||
|
@ -225,6 +226,9 @@ class MetaSimObject(type):
|
|||
cls._value_dict['swig_predecls'] = \
|
||||
cls._value_dict['cxx_predecls']
|
||||
|
||||
if 'swig_objdecls' not in cls._value_dict:
|
||||
cls._value_dict['swig_objdecls'] = []
|
||||
|
||||
# Now process the _value_dict items. They could be defining
|
||||
# new (or overriding existing) parameters or ports, setting
|
||||
# class keywords (e.g., 'abstract'), or setting parameter
|
||||
|
@ -345,12 +349,13 @@ class MetaSimObject(type):
|
|||
def __str__(cls):
|
||||
return cls.__name__
|
||||
|
||||
def cxx_decl(cls):
|
||||
if str(cls) != 'SimObject':
|
||||
base = cls.__bases__[0].type
|
||||
else:
|
||||
base = None
|
||||
def get_base(cls):
|
||||
if str(cls) == 'SimObject':
|
||||
return None
|
||||
|
||||
return cls.__bases__[0].type
|
||||
|
||||
def cxx_decl(cls):
|
||||
code = "#ifndef __PARAMS__%s\n" % cls
|
||||
code += "#define __PARAMS__%s\n\n" % cls
|
||||
|
||||
|
@ -380,6 +385,7 @@ class MetaSimObject(type):
|
|||
code += "\n".join(predecls2)
|
||||
code += "\n\n";
|
||||
|
||||
base = cls.get_base()
|
||||
if base:
|
||||
code += '#include "params/%s.hh"\n\n' % base
|
||||
|
||||
|
@ -408,11 +414,7 @@ class MetaSimObject(type):
|
|||
return code
|
||||
|
||||
def cxx_type_decl(cls):
|
||||
if str(cls) != 'SimObject':
|
||||
base = cls.__bases__[0]
|
||||
else:
|
||||
base = None
|
||||
|
||||
base = cls.get_base()
|
||||
code = ''
|
||||
|
||||
if base:
|
||||
|
@ -427,17 +429,14 @@ class MetaSimObject(type):
|
|||
return code
|
||||
|
||||
def swig_decl(cls):
|
||||
base = cls.get_base()
|
||||
|
||||
code = '%%module %s\n' % cls
|
||||
|
||||
code += '%{\n'
|
||||
code += '#include "params/%s.hh"\n' % cls
|
||||
code += '%}\n\n'
|
||||
|
||||
if str(cls) != 'SimObject':
|
||||
base = cls.__bases__[0]
|
||||
else:
|
||||
base = None
|
||||
|
||||
# The 'dict' attribute restricts us to the params declared in
|
||||
# the object itself, not including inherited params (which
|
||||
# will also be inherited from the base class's param struct
|
||||
|
@ -483,6 +482,7 @@ class SimObject(object):
|
|||
abstract = True
|
||||
|
||||
name = Param.String("Object name")
|
||||
swig_objdecls = [ '%include "python/swig/sim_object.i"' ]
|
||||
|
||||
# Initialize new instance. For objects with SimObject-valued
|
||||
# children, we need to recursively clone the classes represented
|
||||
|
@ -792,7 +792,6 @@ class SimObject(object):
|
|||
# necessary to construct it. Does *not* recursively create
|
||||
# children.
|
||||
def getCCObject(self):
|
||||
import internal
|
||||
params = self.getCCParams()
|
||||
if not self._ccObject:
|
||||
self._ccObject = -1 # flag to catch cycles in recursion
|
||||
|
@ -840,24 +839,19 @@ class SimObject(object):
|
|||
if not isinstance(self, m5.objects.System):
|
||||
return None
|
||||
|
||||
system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject)
|
||||
return system_ptr.getMemoryMode()
|
||||
return self._ccObject.getMemoryMode()
|
||||
|
||||
def changeTiming(self, mode):
|
||||
import internal
|
||||
if isinstance(self, m5.objects.System):
|
||||
# i don't know if there's a better way to do this - calling
|
||||
# setMemoryMode directly from self._ccObject results in calling
|
||||
# SimObject::setMemoryMode, not the System::setMemoryMode
|
||||
system_ptr = internal.sim_object.convertToSystemPtr(self._ccObject)
|
||||
system_ptr.setMemoryMode(mode)
|
||||
self._ccObject.setMemoryMode(mode)
|
||||
for child in self._children.itervalues():
|
||||
child.changeTiming(mode)
|
||||
|
||||
def takeOverFrom(self, old_cpu):
|
||||
import internal
|
||||
cpu_ptr = internal.sim_object.convertToBaseCPUPtr(old_cpu._ccObject)
|
||||
self._ccObject.takeOverFrom(cpu_ptr)
|
||||
self._ccObject.takeOverFrom(old_cpu._ccObject)
|
||||
|
||||
# generate output file for 'dot' to display as a pretty graph.
|
||||
# this code is currently broken.
|
||||
|
|
|
@ -81,11 +81,6 @@ try:
|
|||
except ImportError:
|
||||
running_m5 = False
|
||||
|
||||
if running_m5:
|
||||
from event import *
|
||||
from simulate import *
|
||||
from main import options
|
||||
|
||||
if running_m5:
|
||||
import defines
|
||||
build_env.update(defines.m5_build_env)
|
||||
|
@ -93,6 +88,11 @@ else:
|
|||
import __scons
|
||||
build_env.update(__scons.m5_build_env)
|
||||
|
||||
if running_m5:
|
||||
from event import *
|
||||
from simulate import *
|
||||
from main import options
|
||||
|
||||
import SimObject
|
||||
import params
|
||||
import objects
|
||||
|
|
|
@ -30,6 +30,5 @@ import core
|
|||
import debug
|
||||
import event
|
||||
import random
|
||||
import sim_object
|
||||
import stats
|
||||
import trace
|
||||
|
|
|
@ -26,9 +26,15 @@
|
|||
#
|
||||
# Authors: Nathan Binkert
|
||||
|
||||
import code, optparse, os, socket, sys
|
||||
from datetime import datetime
|
||||
import code
|
||||
import datetime
|
||||
import optparse
|
||||
import os
|
||||
import socket
|
||||
import sys
|
||||
|
||||
from attrdict import attrdict
|
||||
import defines
|
||||
import traceflags
|
||||
|
||||
__all__ = [ 'options', 'arguments', 'main' ]
|
||||
|
@ -116,6 +122,8 @@ def bool_option(name, default, help):
|
|||
# Help options
|
||||
add_option('-A', "--authors", action="store_true", default=False,
|
||||
help="Show author information")
|
||||
add_option('-B', "--build-info", action="store_true", default=False,
|
||||
help="Show build information")
|
||||
add_option('-C', "--copyright", action="store_true", default=False,
|
||||
help="Show full copyright information")
|
||||
add_option('-R', "--readme", action="store_true", default=False,
|
||||
|
@ -195,6 +203,22 @@ def main():
|
|||
parse_args()
|
||||
|
||||
done = False
|
||||
|
||||
if options.build_info:
|
||||
done = True
|
||||
print 'Build information:'
|
||||
print
|
||||
print 'compiled %s' % internal.core.cvar.compileDate;
|
||||
print 'started %s' % datetime.datetime.now().ctime()
|
||||
print 'executing on %s' % socket.gethostname()
|
||||
print 'build options:'
|
||||
keys = defines.m5_build_env.keys()
|
||||
keys.sort()
|
||||
for key in keys:
|
||||
val = defines.m5_build_env[key]
|
||||
print ' %s = %s' % (key, val)
|
||||
print
|
||||
|
||||
if options.copyright:
|
||||
done = True
|
||||
print info.LICENSE
|
||||
|
@ -242,7 +266,7 @@ def main():
|
|||
print brief_copyright
|
||||
print
|
||||
print "M5 compiled %s" % internal.core.cvar.compileDate;
|
||||
print "M5 started %s" % datetime.now().ctime()
|
||||
print "M5 started %s" % datetime.datetime.now().ctime()
|
||||
print "M5 executing on %s" % socket.gethostname()
|
||||
print "command line:",
|
||||
for argv in sys.argv:
|
||||
|
|
|
@ -1025,13 +1025,13 @@ class PortRef(object):
|
|||
|
||||
# Call C++ to create corresponding port connection between C++ objects
|
||||
def ccConnect(self):
|
||||
import internal
|
||||
from m5.objects.params import connectPorts
|
||||
|
||||
if self.ccConnected: # already done this
|
||||
return
|
||||
peer = self.peer
|
||||
internal.sim_object.connectPorts(self.simobj.getCCObject(), self.name,
|
||||
self.index, peer.simobj.getCCObject(), peer.name, peer.index)
|
||||
connectPorts(self.simobj.getCCObject(), self.name, self.index,
|
||||
peer.simobj.getCCObject(), peer.name, peer.index)
|
||||
self.ccConnected = True
|
||||
peer.ccConnected = True
|
||||
|
||||
|
|
|
@ -36,6 +36,7 @@ import internal
|
|||
from main import options
|
||||
import SimObject
|
||||
import ticks
|
||||
import objects
|
||||
|
||||
# The final hook to generate .ini files. Called from the user script
|
||||
# once the config is built.
|
||||
|
@ -58,10 +59,10 @@ def instantiate(root):
|
|||
root.connectPorts()
|
||||
|
||||
# Do a second pass to finish initializing the sim objects
|
||||
internal.sim_object.initAll()
|
||||
internal.core.initAll()
|
||||
|
||||
# Do a third pass to initialize statistics
|
||||
internal.sim_object.regAllStats()
|
||||
internal.core.regAllStats()
|
||||
|
||||
# Check to make sure that the stats package is properly initialized
|
||||
internal.stats.check()
|
||||
|
@ -135,32 +136,32 @@ def checkpoint(root, dir):
|
|||
raise TypeError, "Checkpoint must be called on a root object."
|
||||
doDrain(root)
|
||||
print "Writing checkpoint"
|
||||
internal.sim_object.serializeAll(dir)
|
||||
internal.core.serializeAll(dir)
|
||||
resume(root)
|
||||
|
||||
def restoreCheckpoint(root, dir):
|
||||
print "Restoring from checkpoint"
|
||||
internal.sim_object.unserializeAll(dir)
|
||||
internal.core.unserializeAll(dir)
|
||||
need_resume.append(root)
|
||||
|
||||
def changeToAtomic(system):
|
||||
if not isinstance(system, (objects.Root, objects.System)):
|
||||
raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
|
||||
(type(system), objects.Root, objects.System)
|
||||
if system.getMemoryMode() != internal.sim_object.SimObject.Atomic:
|
||||
if system.getMemoryMode() != objects.params.SimObject.Atomic:
|
||||
doDrain(system)
|
||||
print "Changing memory mode to atomic"
|
||||
system.changeTiming(internal.sim_object.SimObject.Atomic)
|
||||
system.changeTiming(objects.params.SimObject.Atomic)
|
||||
|
||||
def changeToTiming(system):
|
||||
if not isinstance(system, (objects.Root, objects.System)):
|
||||
raise TypeError, "Parameter of type '%s'. Must be type %s or %s." % \
|
||||
(type(system), objects.Root, objects.System)
|
||||
|
||||
if system.getMemoryMode() != internal.sim_object.SimObject.Timing:
|
||||
if system.getMemoryMode() != objects.params.SimObject.Timing:
|
||||
doDrain(system)
|
||||
print "Changing memory mode to timing"
|
||||
system.changeTiming(internal.sim_object.SimObject.Timing)
|
||||
system.changeTiming(objects.params.SimObject.Timing)
|
||||
|
||||
def switchCpus(cpuList):
|
||||
print "switching cpus"
|
||||
|
|
|
@ -58,6 +58,12 @@ void setClockFrequency(Tick ticksPerSecond);
|
|||
%immutable curTick;
|
||||
Tick curTick;
|
||||
|
||||
void serializeAll(const std::string &cpt_dir);
|
||||
void unserializeAll(const std::string &cpt_dir);
|
||||
|
||||
void initAll();
|
||||
void regAllStats();
|
||||
|
||||
%wrapper %{
|
||||
// fix up module name to reflect the fact that it's inside the m5 package
|
||||
#undef SWIG_name
|
||||
|
|
|
@ -47,26 +47,6 @@ void loadIniFile(PyObject *_resolveFunc);
|
|||
int connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2);
|
||||
|
||||
inline BaseCPU *
|
||||
convertToBaseCPUPtr(SimObject *obj)
|
||||
{
|
||||
BaseCPU *ptr = dynamic_cast<BaseCPU *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to BaseCPU pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
inline System *
|
||||
convertToSystemPtr(SimObject *obj)
|
||||
{
|
||||
System *ptr = dynamic_cast<System *>(obj);
|
||||
|
||||
if (ptr == NULL)
|
||||
warn("Casting to System pointer failed");
|
||||
return ptr;
|
||||
}
|
||||
|
||||
inline void
|
||||
initAll()
|
||||
{
|
||||
|
|
|
@ -31,7 +31,6 @@
|
|||
%module sim_object
|
||||
|
||||
%{
|
||||
#include "enums/MemoryMode.hh"
|
||||
#include "python/swig/pyobject.hh"
|
||||
%}
|
||||
|
||||
|
@ -57,31 +56,10 @@ class SimObject {
|
|||
SimObject(const std::string &_name);
|
||||
};
|
||||
|
||||
class System {
|
||||
private:
|
||||
System();
|
||||
public:
|
||||
Enums::MemoryMode getMemoryMode();
|
||||
void setMemoryMode(Enums::MemoryMode mode);
|
||||
};
|
||||
|
||||
int connectPorts(SimObject *o1, const std::string &name1, int i1,
|
||||
SimObject *o2, const std::string &name2, int i2);
|
||||
|
||||
BaseCPU *convertToBaseCPUPtr(SimObject *obj);
|
||||
System *convertToSystemPtr(SimObject *obj);
|
||||
|
||||
void serializeAll(const std::string &cpt_dir);
|
||||
void unserializeAll(const std::string &cpt_dir);
|
||||
|
||||
void initAll();
|
||||
void regAllStats();
|
||||
|
||||
%wrapper %{
|
||||
// fix up module name to reflect the fact that it's inside the m5 package
|
||||
#undef SWIG_name
|
||||
#define SWIG_name "m5.internal._sim_object"
|
||||
|
||||
// Convert a pointer to the Python object that SWIG wraps around a
|
||||
// C++ SimObject pointer back to the actual C++ pointer.
|
||||
SimObject *
|
||||
|
|
43
src/python/swig/system.i
Normal file
43
src/python/swig/system.i
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (c) 2006 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Nathan Binkert
|
||||
*/
|
||||
|
||||
%module sim_object
|
||||
|
||||
%include "enums/MemoryMode.hh"
|
||||
|
||||
class System : public SimObject
|
||||
{
|
||||
private:
|
||||
System();
|
||||
public:
|
||||
Enums::MemoryMode getMemoryMode();
|
||||
void setMemoryMode(Enums::MemoryMode mode);
|
||||
};
|
||||
|
|
@ -36,6 +36,8 @@ class MemoryMode(Enum): vals = ['invalid', 'atomic', 'timing']
|
|||
|
||||
class System(SimObject):
|
||||
type = 'System'
|
||||
swig_objdecls = [ '%include "python/swig/system.i"' ]
|
||||
|
||||
physmem = Param.PhysicalMemory(Parent.any, "phsyical memory")
|
||||
mem_mode = Param.MemoryMode('atomic', "The mode the memory system is in")
|
||||
if build_env['FULL_SYSTEM']:
|
||||
|
|
|
@ -178,6 +178,22 @@ paramOut(ostream &os, const std::string &name, const T ¶m)
|
|||
os << "\n";
|
||||
}
|
||||
|
||||
template <class T>
|
||||
void
|
||||
arrayParamOut(ostream &os, const std::string &name,
|
||||
const std::vector<T> ¶m)
|
||||
{
|
||||
int size = param.size();
|
||||
os << name << "=";
|
||||
if (size > 0)
|
||||
showParam(os, param[0]);
|
||||
for (int i = 1; i < size; ++i) {
|
||||
os << " ";
|
||||
showParam(os, param[i]);
|
||||
}
|
||||
os << "\n";
|
||||
}
|
||||
|
||||
|
||||
template <class T>
|
||||
void
|
||||
|
@ -251,6 +267,49 @@ arrayParamIn(Checkpoint *cp, const std::string §ion,
|
|||
}
|
||||
}
|
||||
|
||||
template <class T>
|
||||
void
|
||||
arrayParamIn(Checkpoint *cp, const std::string §ion,
|
||||
const std::string &name, std::vector<T> ¶m)
|
||||
{
|
||||
std::string str;
|
||||
if (!cp->find(section, name, str)) {
|
||||
fatal("Can't unserialize '%s:%s'\n", section, name);
|
||||
}
|
||||
|
||||
// code below stolen from VectorParam<T>::parse().
|
||||
// it would be nice to unify these somehow...
|
||||
|
||||
vector<string> tokens;
|
||||
|
||||
tokenize(tokens, str, ' ');
|
||||
|
||||
// Need this if we were doing a vector
|
||||
// value.resize(tokens.size());
|
||||
|
||||
param.resize(tokens.size());
|
||||
|
||||
for (int i = 0; i < tokens.size(); i++) {
|
||||
// need to parse into local variable to handle vector<bool>,
|
||||
// for which operator[] returns a special reference class
|
||||
// that's not the same as 'bool&', (since it's a packed
|
||||
// vector)
|
||||
T scalar_value;
|
||||
if (!parseParam(tokens[i], scalar_value)) {
|
||||
string err("could not parse \"");
|
||||
|
||||
err += str;
|
||||
err += "\"";
|
||||
|
||||
fatal(err);
|
||||
}
|
||||
|
||||
// assign parsed value to vector
|
||||
param[i] = scalar_value;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
void
|
||||
objParamIn(Checkpoint *cp, const std::string §ion,
|
||||
|
@ -273,7 +332,13 @@ arrayParamOut(ostream &os, const std::string &name, \
|
|||
type const *param, int size); \
|
||||
template void \
|
||||
arrayParamIn(Checkpoint *cp, const std::string §ion, \
|
||||
const std::string &name, type *param, int size);
|
||||
const std::string &name, type *param, int size); \
|
||||
template void \
|
||||
arrayParamOut(ostream &os, const std::string &name, \
|
||||
const std::vector<type> ¶m); \
|
||||
template void \
|
||||
arrayParamIn(Checkpoint *cp, const std::string §ion, \
|
||||
const std::string &name, std::vector<type> ¶m);
|
||||
|
||||
INSTANTIATE_PARAM_TEMPLATES(signed char)
|
||||
INSTANTIATE_PARAM_TEMPLATES(unsigned char)
|
||||
|
@ -358,7 +423,6 @@ Serializable::unserializeAll(const std::string &cpt_dir)
|
|||
dir);
|
||||
Checkpoint *cp = new Checkpoint(dir, section);
|
||||
unserializeGlobals(cp);
|
||||
|
||||
SimObject::unserializeAll(cp);
|
||||
}
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
|
||||
|
||||
#include <list>
|
||||
#include <vector>
|
||||
#include <iostream>
|
||||
#include <map>
|
||||
|
||||
|
@ -60,10 +61,18 @@ template <class T>
|
|||
void arrayParamOut(std::ostream &os, const std::string &name,
|
||||
const T *param, int size);
|
||||
|
||||
template <class T>
|
||||
void arrayParamOut(std::ostream &os, const std::string &name,
|
||||
const std::vector<T> ¶m);
|
||||
|
||||
template <class T>
|
||||
void arrayParamIn(Checkpoint *cp, const std::string §ion,
|
||||
const std::string &name, T *param, int size);
|
||||
|
||||
template <class T>
|
||||
void arrayParamIn(Checkpoint *cp, const std::string §ion,
|
||||
const std::string &name, std::vector<T> ¶m);
|
||||
|
||||
void
|
||||
objParamIn(Checkpoint *cp, const std::string §ion,
|
||||
const std::string &name, SimObject * ¶m);
|
||||
|
|
|
@ -72,7 +72,8 @@ System::System(Params *p)
|
|||
|
||||
#if FULL_SYSTEM
|
||||
kernelSymtab = new SymbolTable;
|
||||
debugSymbolTable = new SymbolTable;
|
||||
if (!debugSymbolTable)
|
||||
debugSymbolTable = new SymbolTable;
|
||||
|
||||
|
||||
/**
|
||||
|
|
Loading…
Reference in a new issue