Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem
tests/long/30.eon/ref/alpha/linux/simple-timing/m5stats.txt:
"Hand merge" that just used the local file.
--HG--
extra : convert_revision : 24c7fa192094958be5a9d17c3461f3328079fd3b
This commit is contained in:
Gabe Black
commit
3afbf306f4
19 changed files with 398 additions and 594 deletions
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@ -186,7 +186,7 @@ cwd=build/ALPHA_SE/tests/fast/long/30.eon/alpha/linux/simple-timing
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egid=100
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env=
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euid=100
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
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executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
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gid=100
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input=cin
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output=cout
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@ -27,7 +27,7 @@ responder_set=false
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[system.cpu.workload]
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type=LiveProcess
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cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
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executable=/dist/m5/cpu2000/binaries/alpha/tru64/eon
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executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/eon
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input=cin
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output=cout
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env=
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@ -1,13 +1,13 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 595543 # Simulator instruction rate (inst/s)
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host_mem_usage 157792 # Number of bytes of host memory used
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host_seconds 669.41 # Real time elapsed on the host
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host_tick_rate 892368 # Simulator tick rate (ticks/s)
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host_inst_rate 689508 # Simulator instruction rate (inst/s)
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host_mem_usage 185012 # Number of bytes of host memory used
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host_seconds 578.19 # Real time elapsed on the host
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host_tick_rate 1033135 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 398664450 # Number of instructions simulated
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sim_seconds 0.000597 # Number of seconds simulated
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sim_ticks 597363012 # Number of ticks simulated
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sim_ticks 597346012 # Number of ticks simulated
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system.cpu.dcache.ReadReq_accesses 94754482 # number of ReadReq accesses(hits+misses)
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system.cpu.dcache.ReadReq_avg_miss_latency 3956.610526 # average ReadReq miss latency
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system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2956.610526 # average ReadReq mshr miss latency
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@ -19,49 +19,49 @@ system.cpu.dcache.ReadReq_mshr_miss_latency 2808780 #
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system.cpu.dcache.ReadReq_mshr_miss_rate 0.000010 # mshr miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_mshr_misses 950 # number of ReadReq MSHR misses
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system.cpu.dcache.WriteReq_accesses 73520727 # number of WriteReq accesses(hits+misses)
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system.cpu.dcache.WriteReq_avg_miss_latency 3939.646399 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2939.646399 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73517520 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 12634446 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_avg_miss_latency 3940.471580 # average WriteReq miss latency
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system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2940.471580 # average WriteReq mshr miss latency
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system.cpu.dcache.WriteReq_hits 73517525 # number of WriteReq hits
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system.cpu.dcache.WriteReq_miss_latency 12617390 # number of WriteReq miss cycles
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system.cpu.dcache.WriteReq_miss_rate 0.000044 # miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_misses 3207 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 9427446 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_misses 3202 # number of WriteReq misses
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system.cpu.dcache.WriteReq_mshr_miss_latency 9415390 # number of WriteReq MSHR miss cycles
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system.cpu.dcache.WriteReq_mshr_miss_rate 0.000044 # mshr miss rate for WriteReq accesses
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system.cpu.dcache.WriteReq_mshr_misses 3207 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40478.963676 # Average number of references to valid blocks.
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system.cpu.dcache.WriteReq_mshr_misses 3202 # number of WriteReq MSHR misses
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system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
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system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
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system.cpu.dcache.avg_refs 40527.711224 # Average number of references to valid blocks.
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system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
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||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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system.cpu.dcache.cache_copies 0 # number of cache copies performed
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system.cpu.dcache.demand_accesses 168275209 # number of demand (read+write) accesses
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||||
system.cpu.dcache.demand_avg_miss_latency 3943.523214 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168271052 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 16393226 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_avg_miss_latency 3944.164258 # average overall miss latency
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system.cpu.dcache.demand_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
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system.cpu.dcache.demand_hits 168271057 # number of demand (read+write) hits
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system.cpu.dcache.demand_miss_latency 16376170 # number of demand (read+write) miss cycles
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system.cpu.dcache.demand_miss_rate 0.000025 # miss rate for demand accesses
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system.cpu.dcache.demand_misses 4157 # number of demand (read+write) misses
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system.cpu.dcache.demand_misses 4152 # number of demand (read+write) misses
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system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
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||||
system.cpu.dcache.demand_mshr_miss_latency 12236226 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_latency 12224170 # number of demand (read+write) MSHR miss cycles
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system.cpu.dcache.demand_mshr_miss_rate 0.000025 # mshr miss rate for demand accesses
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system.cpu.dcache.demand_mshr_misses 4157 # number of demand (read+write) MSHR misses
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system.cpu.dcache.demand_mshr_misses 4152 # number of demand (read+write) MSHR misses
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system.cpu.dcache.fast_writes 0 # number of fast writes performed
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||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
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||||
system.cpu.dcache.overall_accesses 168275209 # number of overall (read+write) accesses
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||||
system.cpu.dcache.overall_avg_miss_latency 3943.523214 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2943.523214 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168271052 # number of overall hits
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system.cpu.dcache.overall_miss_latency 16393226 # number of overall miss cycles
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system.cpu.dcache.overall_avg_miss_latency 3944.164258 # average overall miss latency
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system.cpu.dcache.overall_avg_mshr_miss_latency 2944.164258 # average overall mshr miss latency
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system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
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system.cpu.dcache.overall_hits 168271057 # number of overall hits
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system.cpu.dcache.overall_miss_latency 16376170 # number of overall miss cycles
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||||
system.cpu.dcache.overall_miss_rate 0.000025 # miss rate for overall accesses
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||||
system.cpu.dcache.overall_misses 4157 # number of overall misses
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system.cpu.dcache.overall_misses 4152 # number of overall misses
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||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12236226 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 12224170 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.000025 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 4157 # number of overall MSHR misses
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||||
system.cpu.dcache.overall_mshr_misses 4152 # number of overall MSHR misses
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||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
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||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
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||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
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@ -74,24 +74,24 @@ system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0
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system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
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system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
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system.cpu.dcache.replacements 764 # number of replacements
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system.cpu.dcache.sampled_refs 4157 # Sample count of references to valid blocks.
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system.cpu.dcache.sampled_refs 4152 # Sample count of references to valid blocks.
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system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
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||||
system.cpu.dcache.tagsinuse 3222.448687 # Cycle average of tags in use
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||||
system.cpu.dcache.total_refs 168271052 # Total number of references to valid blocks.
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system.cpu.dcache.tagsinuse 3222.413784 # Cycle average of tags in use
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||||
system.cpu.dcache.total_refs 168271057 # Total number of references to valid blocks.
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system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
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system.cpu.dcache.writebacks 625 # number of writebacks
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system.cpu.icache.ReadReq_accesses 398664451 # number of ReadReq accesses(hits+misses)
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||||
system.cpu.icache.ReadReq_avg_miss_latency 3820.892216 # average ReadReq miss latency
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||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.892216 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_avg_miss_latency 3820.906097 # average ReadReq miss latency
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system.cpu.icache.ReadReq_avg_mshr_miss_latency 2820.906097 # average ReadReq mshr miss latency
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system.cpu.icache.ReadReq_hits 398660777 # number of ReadReq hits
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system.cpu.icache.ReadReq_miss_latency 14037958 # number of ReadReq miss cycles
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||||
system.cpu.icache.ReadReq_miss_latency 14038009 # number of ReadReq miss cycles
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||||
system.cpu.icache.ReadReq_miss_rate 0.000009 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 3674 # number of ReadReq misses
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||||
system.cpu.icache.ReadReq_mshr_miss_latency 10363958 # number of ReadReq MSHR miss cycles
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||||
system.cpu.icache.ReadReq_mshr_miss_latency 10364009 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000009 # mshr miss rate for ReadReq accesses
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||||
system.cpu.icache.ReadReq_mshr_misses 3674 # number of ReadReq MSHR misses
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||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
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||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
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system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
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||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 108508.649156 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
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||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
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||||
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@ -99,29 +99,29 @@ system.cpu.icache.blocked_cycles_no_mshrs 0 # n
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system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
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||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 398664451 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3820.892216 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_avg_miss_latency 3820.906097 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 398660777 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 14037958 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_latency 14038009 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000009 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 3674 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 10363958 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 10364009 # number of demand (read+write) MSHR miss cycles
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||||
system.cpu.icache.demand_mshr_miss_rate 0.000009 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 3674 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 398664451 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3820.892216 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2820.892216 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_avg_miss_latency 3820.906097 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2820.906097 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 398660777 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 14037958 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_latency 14038009 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000009 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 3674 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 10363958 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 10364009 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000009 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 3674 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
|
|
@ -138,57 +138,57 @@ system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0
|
|||
system.cpu.icache.replacements 1770 # number of replacements
|
||||
system.cpu.icache.sampled_refs 3674 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1765.884663 # Cycle average of tags in use
|
||||
system.cpu.icache.tagsinuse 1765.882838 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 398660777 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 7831 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2982.860028 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.618942 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 7826 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2983.265505 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1924.984530 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 651 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21416935 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916869 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7180 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13818764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916869 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7180 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.ReadReq_miss_latency 21404930 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.916816 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 7175 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 13811764 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.916816 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 7175 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 625 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 625 # number of Writeback hits
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177716 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.177840 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 7831 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2982.860028 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 7826 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 651 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 21416935 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916869 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7180 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_miss_latency 21404930 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.916816 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 7175 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13818764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916869 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7180 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 13811764 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.916816 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 7175 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 8456 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2982.860028 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.618942 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_accesses 8451 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2983.265505 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1924.984530 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 1276 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 21416935 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.849101 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7180 # number of overall misses
|
||||
system.cpu.l2cache.overall_miss_latency 21404930 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.849012 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 7175 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13818764 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.849101 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7180 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 13811764 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.849012 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 7175 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -201,14 +201,14 @@ system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 0 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 7180 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.sampled_refs 7175 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 6344.085280 # Cycle average of tags in use
|
||||
system.cpu.l2cache.tagsinuse 6344.042673 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 1276 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 0 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 597363012 # number of cpu cycles simulated
|
||||
system.cpu.numCycles 597346012 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 398664450 # Number of instructions executed
|
||||
system.cpu.num_refs 174183390 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 215 # Number of system calls
|
||||
|
|
|
|||
|
|
@ -7,21 +7,6 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
|
|
@ -74,11 +59,11 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
@ -100,14 +85,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=PhysicalMemory
|
|||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -26,11 +27,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -57,15 +58,6 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
|
|
@ -83,25 +75,6 @@ dump_cycle=0
|
|||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 906784 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 147280 # Number of bytes of host memory used
|
||||
host_seconds 2215.51 # Real time elapsed on the host
|
||||
host_tick_rate 906784 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1149393 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 177516 # Number of bytes of host memory used
|
||||
host_seconds 1747.87 # Real time elapsed on the host
|
||||
host_tick_rate 1149393 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987724 # Number of instructions simulated
|
||||
sim_insts 2008987607 # Number of instructions simulated
|
||||
sim_seconds 0.002009 # Number of seconds simulated
|
||||
sim_ticks 2008987723 # Number of ticks simulated
|
||||
sim_ticks 2008987606 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 2008987724 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987724 # Number of instructions executed
|
||||
system.cpu.num_refs 722390480 # Number of memory references
|
||||
system.cpu.numCycles 2008987607 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987607 # Number of instructions executed
|
||||
system.cpu.num_refs 722390435 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
|
|
@ -7,21 +7,6 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
|
|
@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
@ -223,14 +208,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=PhysicalMemory
|
|||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -26,11 +27,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=perlbmk -I. -I lib lgred.makerand.pl
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/perlbmk
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/40.perlbmk/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/40.perlbmk/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -178,15 +179,6 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
|
|
@ -204,25 +196,6 @@ dump_cycle=0
|
|||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 502967 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 217744 # Number of bytes of host memory used
|
||||
host_seconds 3994.27 # Real time elapsed on the host
|
||||
host_tick_rate 1895851 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 752631 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 230876 # Number of bytes of host memory used
|
||||
host_seconds 2669.29 # Real time elapsed on the host
|
||||
host_tick_rate 2836913 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 2008987724 # Number of instructions simulated
|
||||
sim_insts 2008987607 # Number of instructions simulated
|
||||
sim_seconds 0.007573 # Number of seconds simulated
|
||||
sim_ticks 7572549003 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070058 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3107.171711 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171711 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611866 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4530852932 # number of ReadReq miss cycles
|
||||
sim_ticks 7572532003 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 511070026 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3107.171986 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2107.171986 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 509611834 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 4530853333 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002853 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 1458192 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3072660932 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 3072661333 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002853 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 1458192 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 210794909 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3884.294897 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.294897 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210722955 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 279490555 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_accesses 210794896 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 3884.267929 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 2884.267929 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 210722944 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 279480846 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.000341 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 71954 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 207536555 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_misses 71952 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 207528846 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.000341 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 71954 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 470.762150 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.WriteReq_mshr_misses 71952 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 470.762737 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 721864967 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3143.715362 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720334821 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4810343487 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_accesses 721864922 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 3143.713388 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 720334778 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 4810334179 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.002120 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 1530146 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_misses 1530144 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3280197487 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_latency 3280190179 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.002120 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 1530146 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_misses 1530144 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 721864967 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3143.715362 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2143.715362 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720334821 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4810343487 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_accesses 721864922 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 3143.713388 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 2143.713388 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 720334778 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 4810334179 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.002120 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 1530146 # number of overall misses
|
||||
system.cpu.dcache.overall_misses 1530144 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3280197487 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_latency 3280190179 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.002120 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 1530146 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_misses 1530144 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 1526050 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530146 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 1526048 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 1530144 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4087.472566 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334821 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 35194000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74591 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2008987725 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3103.752500 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.752500 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2008977127 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32893569 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.tagsinuse 4087.479154 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 720334778 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 35165000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 74589 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 2008987608 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 3103.627312 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 2103.627312 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 2008977012 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 32886035 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000005 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 10598 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 22295569 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_misses 10596 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 22290035 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000005 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 10598 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 189561.910455 # Average number of references to valid blocks.
|
||||
system.cpu.icache.ReadReq_mshr_misses 10596 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 189597.679502 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 2008987725 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3103.752500 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2008977127 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32893569 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_accesses 2008987608 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 3103.627312 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 2008977012 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 32886035 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000005 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 10598 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_misses 10596 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 22295569 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_latency 22290035 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000005 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 10598 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_misses 10596 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 2008987725 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3103.752500 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2103.752500 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2008977127 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32893569 # number of overall miss cycles
|
||||
system.cpu.icache.overall_accesses 2008987608 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 3103.627312 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 2103.627312 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 2008977012 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 32886035 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000005 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 10598 # number of overall misses
|
||||
system.cpu.icache.overall_misses 10596 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 22295569 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_latency 22290035 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000005 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 10598 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_misses 10596 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 9048 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10598 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 9046 # number of replacements
|
||||
system.cpu.icache.sampled_refs 10596 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1472.251444 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2008977127 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1471.254279 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 2008977012 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 1540744 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2153.831026 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.660796 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_accesses 1540740 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 2153.828221 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1111.659139 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 33878 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 3245534743 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_latency 3245521901 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.978012 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 1506866 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1675123857 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_misses 1506862 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 1675116913 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.978012 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1506866 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 74591 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 73517 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.014399 # miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_misses 1074 # number of WriteReqNoAck|Writeback misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.014399 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 1074 # number of WriteReqNoAck|Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.071270 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 1506862 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 74589 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 73515 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.014399 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 1074 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.014399 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 1074 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 0.071269 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 1540744 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2153.831026 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_accesses 1540740 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 2153.828221 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 33878 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 3245534743 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_latency 3245521901 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.978012 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 1506866 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_misses 1506862 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1675123857 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 1675116913 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.978012 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 1506866 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_misses 1506862 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 1615335 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2152.297003 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.660796 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 107395 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3245534743 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.933515 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1507940 # number of overall misses
|
||||
system.cpu.l2cache.overall_accesses 1615329 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 2152.294196 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1111.659139 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 107393 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 3245521901 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.933516 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 1507936 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1675123857 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.932850 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1506866 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 1675116913 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.932851 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 1506862 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 1474098 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506866 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 1474094 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 1506862 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 32444.673070 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 107395 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 164218000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66806 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 32444.706916 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 107393 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 164189000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 66804 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 7572549003 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987724 # Number of instructions executed
|
||||
system.cpu.num_refs 722390480 # Number of memory references
|
||||
system.cpu.numCycles 7572532003 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 2008987607 # Number of instructions executed
|
||||
system.cpu.num_refs 722390435 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 39 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1,2 +1,3 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
warn: ignoring syscall sigprocmask(1, 0, ...)
|
||||
|
|
|
|||
|
|
@ -7,21 +7,6 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
|
|
@ -74,11 +59,11 @@ icache_port=system.membus.port[1]
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
@ -100,14 +85,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=PhysicalMemory
|
|||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -26,11 +27,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-atomic
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-atomic
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -57,15 +58,6 @@ function_trace=false
|
|||
function_trace_start=0
|
||||
simulate_stalls=false
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
|
|
@ -83,25 +75,6 @@ dump_cycle=0
|
|||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,18 +1,18 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 857494 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 149092 # Number of bytes of host memory used
|
||||
host_seconds 103.05 # Real time elapsed on the host
|
||||
host_tick_rate 857491 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 1347543 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 179988 # Number of bytes of host memory used
|
||||
host_seconds 65.56 # Real time elapsed on the host
|
||||
host_tick_rate 1347535 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88361899 # Number of instructions simulated
|
||||
sim_insts 88340674 # Number of instructions simulated
|
||||
sim_seconds 0.000088 # Number of seconds simulated
|
||||
sim_ticks 88361898 # Number of ticks simulated
|
||||
sim_ticks 88340673 # Number of ticks simulated
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 88361899 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88361899 # Number of instructions executed
|
||||
system.cpu.num_refs 35229376 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
|
||||
system.cpu.numCycles 88340674 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340674 # Number of instructions executed
|
||||
system.cpu.num_refs 35224019 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
|
|
@ -7,21 +7,6 @@ max_tick=0
|
|||
output_file=cout
|
||||
progress_interval=0
|
||||
|
||||
[exetrace]
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
pc_symbol=true
|
||||
print_cpseq=false
|
||||
print_cycle=true
|
||||
print_data=true
|
||||
print_effaddr=true
|
||||
print_fetchseq=false
|
||||
print_iregs=false
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
speculative=true
|
||||
trace_system=client
|
||||
|
||||
[serialize]
|
||||
count=10
|
||||
cycle=0
|
||||
|
|
@ -197,11 +182,11 @@ port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cp
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
|
||||
egid=100
|
||||
env=
|
||||
euid=100
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
gid=100
|
||||
input=cin
|
||||
output=cout
|
||||
|
|
@ -223,14 +208,6 @@ type=PhysicalMemory
|
|||
file=
|
||||
latency=1
|
||||
range=0:134217727
|
||||
zero=false
|
||||
port=system.membus.port[0]
|
||||
|
||||
[trace]
|
||||
bufsize=0
|
||||
cycle=0
|
||||
dump_on_exit=false
|
||||
file=cout
|
||||
flags=
|
||||
ignore=
|
||||
start=0
|
||||
|
||||
|
|
|
|||
|
|
@ -10,6 +10,7 @@ type=PhysicalMemory
|
|||
file=
|
||||
range=[0,134217727]
|
||||
latency=1
|
||||
zero=false
|
||||
|
||||
[system]
|
||||
type=System
|
||||
|
|
@ -26,11 +27,11 @@ responder_set=false
|
|||
[system.cpu.workload]
|
||||
type=LiveProcess
|
||||
cmd=vortex lendian.raw
|
||||
executable=/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
executable=/home/gblack/m5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
|
||||
input=cin
|
||||
output=cout
|
||||
env=
|
||||
cwd=build/ALPHA_SE/tests/opt/long/50.vortex/alpha/linux/simple-timing
|
||||
cwd=build/ALPHA_SE/tests/fast/long/50.vortex/alpha/linux/simple-timing
|
||||
system=system
|
||||
uid=100
|
||||
euid=100
|
||||
|
|
@ -178,15 +179,6 @@ prefetch_use_cpu_id=true
|
|||
prefetch_data_accesses_only=false
|
||||
hit_latency=1
|
||||
|
||||
[trace]
|
||||
flags=
|
||||
start=0
|
||||
cycle=0
|
||||
bufsize=0
|
||||
file=cout
|
||||
dump_on_exit=false
|
||||
ignore=
|
||||
|
||||
[stats]
|
||||
descriptions=true
|
||||
project_name=test
|
||||
|
|
@ -204,25 +196,6 @@ dump_cycle=0
|
|||
dump_period=0
|
||||
ignore_events=
|
||||
|
||||
[random]
|
||||
seed=1
|
||||
|
||||
[exetrace]
|
||||
speculative=true
|
||||
print_cycle=true
|
||||
print_opclass=true
|
||||
print_thread=true
|
||||
print_effaddr=true
|
||||
print_data=true
|
||||
print_iregs=false
|
||||
print_fetchseq=false
|
||||
print_cpseq=false
|
||||
print_reg_delta=false
|
||||
pc_symbol=true
|
||||
intel_format=false
|
||||
legion_lockstep=false
|
||||
trace_system=client
|
||||
|
||||
[statsreset]
|
||||
reset_cycle=0
|
||||
|
||||
|
|
|
|||
|
|
@ -1,67 +1,67 @@
|
|||
|
||||
---------- Begin Simulation Statistics ----------
|
||||
host_inst_rate 471701 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 255440 # Number of bytes of host memory used
|
||||
host_seconds 187.33 # Real time elapsed on the host
|
||||
host_tick_rate 6446013 # Simulator tick rate (ticks/s)
|
||||
host_inst_rate 704446 # Simulator instruction rate (inst/s)
|
||||
host_mem_usage 275648 # Number of bytes of host memory used
|
||||
host_seconds 125.40 # Real time elapsed on the host
|
||||
host_tick_rate 9716991 # Simulator tick rate (ticks/s)
|
||||
sim_freq 1000000000000 # Frequency of simulated ticks
|
||||
sim_insts 88361899 # Number of instructions simulated
|
||||
sim_seconds 0.001208 # Number of seconds simulated
|
||||
sim_ticks 1207510003 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20281385 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3631.637073 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2631.637073 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20223321 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 210867375 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002863 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 58064 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 152803375 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002863 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 58064 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14615683 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4569.538784 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3569.538784 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14473602 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 649244640 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009721 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 142081 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 507163640 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009721 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 142081 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 173.358930 # Average number of references to valid blocks.
|
||||
sim_insts 88340674 # Number of instructions simulated
|
||||
sim_seconds 0.001219 # Number of seconds simulated
|
||||
sim_ticks 1218558003 # Number of ticks simulated
|
||||
system.cpu.dcache.ReadReq_accesses 20276638 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.dcache.ReadReq_avg_miss_latency 3613.021476 # average ReadReq miss latency
|
||||
system.cpu.dcache.ReadReq_avg_mshr_miss_latency 2613.021476 # average ReadReq mshr miss latency
|
||||
system.cpu.dcache.ReadReq_hits 20215873 # number of ReadReq hits
|
||||
system.cpu.dcache.ReadReq_miss_latency 219545250 # number of ReadReq miss cycles
|
||||
system.cpu.dcache.ReadReq_miss_rate 0.002997 # miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_misses 60765 # number of ReadReq misses
|
||||
system.cpu.dcache.ReadReq_mshr_miss_latency 158780250 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.dcache.ReadReq_mshr_miss_rate 0.002997 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.dcache.ReadReq_mshr_misses 60765 # number of ReadReq MSHR misses
|
||||
system.cpu.dcache.WriteReq_accesses 14613377 # number of WriteReq accesses(hits+misses)
|
||||
system.cpu.dcache.WriteReq_avg_miss_latency 4540.238491 # average WriteReq miss latency
|
||||
system.cpu.dcache.WriteReq_avg_mshr_miss_latency 3540.238491 # average WriteReq mshr miss latency
|
||||
system.cpu.dcache.WriteReq_hits 14469799 # number of WriteReq hits
|
||||
system.cpu.dcache.WriteReq_miss_latency 651878362 # number of WriteReq miss cycles
|
||||
system.cpu.dcache.WriteReq_miss_rate 0.009825 # miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_misses 143578 # number of WriteReq misses
|
||||
system.cpu.dcache.WriteReq_mshr_miss_latency 508300362 # number of WriteReq MSHR miss cycles
|
||||
system.cpu.dcache.WriteReq_mshr_miss_rate 0.009825 # mshr miss rate for WriteReq accesses
|
||||
system.cpu.dcache.WriteReq_mshr_misses 143578 # number of WriteReq MSHR misses
|
||||
system.cpu.dcache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.dcache.avg_refs 169.742404 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.dcache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.dcache.demand_accesses 34897068 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4297.444428 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34696923 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 860112015 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005735 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 200145 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_accesses 34890015 # number of demand (read+write) accesses
|
||||
system.cpu.dcache.demand_avg_miss_latency 4264.514136 # average overall miss latency
|
||||
system.cpu.dcache.demand_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
|
||||
system.cpu.dcache.demand_hits 34685672 # number of demand (read+write) hits
|
||||
system.cpu.dcache.demand_miss_latency 871423612 # number of demand (read+write) miss cycles
|
||||
system.cpu.dcache.demand_miss_rate 0.005857 # miss rate for demand accesses
|
||||
system.cpu.dcache.demand_misses 204343 # number of demand (read+write) misses
|
||||
system.cpu.dcache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.dcache.demand_mshr_miss_latency 659967015 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005735 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 200145 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.demand_mshr_miss_latency 667080612 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.dcache.demand_mshr_miss_rate 0.005857 # mshr miss rate for demand accesses
|
||||
system.cpu.dcache.demand_mshr_misses 204343 # number of demand (read+write) MSHR misses
|
||||
system.cpu.dcache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.dcache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.dcache.overall_accesses 34897068 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4297.444428 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3297.444428 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34696923 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 860112015 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005735 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 200145 # number of overall misses
|
||||
system.cpu.dcache.overall_accesses 34890015 # number of overall (read+write) accesses
|
||||
system.cpu.dcache.overall_avg_miss_latency 4264.514136 # average overall miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_miss_latency 3264.514136 # average overall mshr miss latency
|
||||
system.cpu.dcache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.dcache.overall_hits 34685672 # number of overall hits
|
||||
system.cpu.dcache.overall_miss_latency 871423612 # number of overall miss cycles
|
||||
system.cpu.dcache.overall_miss_rate 0.005857 # miss rate for overall accesses
|
||||
system.cpu.dcache.overall_misses 204343 # number of overall misses
|
||||
system.cpu.dcache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.dcache.overall_mshr_miss_latency 659967015 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005735 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 200145 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_miss_latency 667080612 # number of overall MSHR miss cycles
|
||||
system.cpu.dcache.overall_mshr_miss_rate 0.005857 # mshr miss rate for overall accesses
|
||||
system.cpu.dcache.overall_mshr_misses 204343 # number of overall MSHR misses
|
||||
system.cpu.dcache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.dcache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -73,57 +73,57 @@ system.cpu.dcache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.dcache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.dcache.replacements 196049 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 200145 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.replacements 200247 # number of replacements
|
||||
system.cpu.dcache.sampled_refs 204343 # Sample count of references to valid blocks.
|
||||
system.cpu.dcache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.dcache.tagsinuse 4056.501584 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34696923 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 28890000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147135 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 88361900 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2933.039863 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1933.039863 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88285387 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 224415679 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000866 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76513 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 147902679 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000866 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76513 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1153.861265 # Average number of references to valid blocks.
|
||||
system.cpu.dcache.tagsinuse 4056.438323 # Cycle average of tags in use
|
||||
system.cpu.dcache.total_refs 34685672 # Total number of references to valid blocks.
|
||||
system.cpu.dcache.warmup_cycle 28900000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.dcache.writebacks 147714 # number of writebacks
|
||||
system.cpu.icache.ReadReq_accesses 88340675 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.icache.ReadReq_avg_miss_latency 2932.969818 # average ReadReq miss latency
|
||||
system.cpu.icache.ReadReq_avg_mshr_miss_latency 1932.969818 # average ReadReq mshr miss latency
|
||||
system.cpu.icache.ReadReq_hits 88264239 # number of ReadReq hits
|
||||
system.cpu.icache.ReadReq_miss_latency 224184481 # number of ReadReq miss cycles
|
||||
system.cpu.icache.ReadReq_miss_rate 0.000865 # miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_misses 76436 # number of ReadReq misses
|
||||
system.cpu.icache.ReadReq_mshr_miss_latency 147748481 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.icache.ReadReq_mshr_miss_rate 0.000865 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.icache.ReadReq_mshr_misses 76436 # number of ReadReq MSHR misses
|
||||
system.cpu.icache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.icache.avg_refs 1154.746965 # Average number of references to valid blocks.
|
||||
system.cpu.icache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.icache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.icache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.icache.demand_accesses 88361900 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2933.039863 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88285387 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 224415679 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000866 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76513 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_accesses 88340675 # number of demand (read+write) accesses
|
||||
system.cpu.icache.demand_avg_miss_latency 2932.969818 # average overall miss latency
|
||||
system.cpu.icache.demand_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
|
||||
system.cpu.icache.demand_hits 88264239 # number of demand (read+write) hits
|
||||
system.cpu.icache.demand_miss_latency 224184481 # number of demand (read+write) miss cycles
|
||||
system.cpu.icache.demand_miss_rate 0.000865 # miss rate for demand accesses
|
||||
system.cpu.icache.demand_misses 76436 # number of demand (read+write) misses
|
||||
system.cpu.icache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.icache.demand_mshr_miss_latency 147902679 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000866 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76513 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.demand_mshr_miss_latency 147748481 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.icache.demand_mshr_miss_rate 0.000865 # mshr miss rate for demand accesses
|
||||
system.cpu.icache.demand_mshr_misses 76436 # number of demand (read+write) MSHR misses
|
||||
system.cpu.icache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.icache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.icache.overall_accesses 88361900 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2933.039863 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1933.039863 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88285387 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 224415679 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000866 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76513 # number of overall misses
|
||||
system.cpu.icache.overall_accesses 88340675 # number of overall (read+write) accesses
|
||||
system.cpu.icache.overall_avg_miss_latency 2932.969818 # average overall miss latency
|
||||
system.cpu.icache.overall_avg_mshr_miss_latency 1932.969818 # average overall mshr miss latency
|
||||
system.cpu.icache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.icache.overall_hits 88264239 # number of overall hits
|
||||
system.cpu.icache.overall_miss_latency 224184481 # number of overall miss cycles
|
||||
system.cpu.icache.overall_miss_rate 0.000865 # miss rate for overall accesses
|
||||
system.cpu.icache.overall_misses 76436 # number of overall misses
|
||||
system.cpu.icache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.icache.overall_mshr_miss_latency 147902679 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000866 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76513 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_miss_latency 147748481 # number of overall MSHR miss cycles
|
||||
system.cpu.icache.overall_mshr_miss_rate 0.000865 # mshr miss rate for overall accesses
|
||||
system.cpu.icache.overall_mshr_misses 76436 # number of overall MSHR misses
|
||||
system.cpu.icache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.icache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.icache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -135,64 +135,64 @@ system.cpu.icache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.icache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.icache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.icache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.icache.replacements 74468 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76513 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.replacements 74391 # number of replacements
|
||||
system.cpu.icache.sampled_refs 76436 # Sample count of references to valid blocks.
|
||||
system.cpu.icache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.icache.tagsinuse 1798.721885 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88285387 # Total number of references to valid blocks.
|
||||
system.cpu.icache.tagsinuse 1796.106842 # Cycle average of tags in use
|
||||
system.cpu.icache.total_refs 88264239 # Total number of references to valid blocks.
|
||||
system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.icache.writebacks 0 # number of writebacks
|
||||
system.cpu.idle_fraction 0 # Percentage of idle cycles
|
||||
system.cpu.l2cache.ReadReq_accesses 276658 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3650.746755 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.771607 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 108220 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 614924482 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.608831 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 168438 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 332289704 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.608831 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 168438 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_accesses 147135 # number of WriteReqNoAck|Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_hits 146550 # number of WriteReqNoAck|Writeback hits
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_miss_rate 0.003976 # miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_misses 585 # number of WriteReqNoAck|Writeback misses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_miss_rate 0.003976 # mshr miss rate for WriteReqNoAck|Writeback accesses
|
||||
system.cpu.l2cache.WriteReqNoAck|Writeback_mshr_misses 585 # number of WriteReqNoAck|Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.512545 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.ReadReq_accesses 280779 # number of ReadReq accesses(hits+misses)
|
||||
system.cpu.l2cache.ReadReq_avg_miss_latency 3650.218185 # average ReadReq miss latency
|
||||
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 1972.851350 # average ReadReq mshr miss latency
|
||||
system.cpu.l2cache.ReadReq_hits 112101 # number of ReadReq hits
|
||||
system.cpu.l2cache.ReadReq_miss_latency 615711503 # number of ReadReq miss cycles
|
||||
system.cpu.l2cache.ReadReq_miss_rate 0.600750 # miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_misses 168678 # number of ReadReq misses
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_latency 332776620 # number of ReadReq MSHR miss cycles
|
||||
system.cpu.l2cache.ReadReq_mshr_miss_rate 0.600750 # mshr miss rate for ReadReq accesses
|
||||
system.cpu.l2cache.ReadReq_mshr_misses 168678 # number of ReadReq MSHR misses
|
||||
system.cpu.l2cache.Writeback_accesses 147714 # number of Writeback accesses(hits+misses)
|
||||
system.cpu.l2cache.Writeback_hits 147276 # number of Writeback hits
|
||||
system.cpu.l2cache.Writeback_miss_rate 0.002965 # miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_misses 438 # number of Writeback misses
|
||||
system.cpu.l2cache.Writeback_mshr_miss_rate 0.002965 # mshr miss rate for Writeback accesses
|
||||
system.cpu.l2cache.Writeback_mshr_misses 438 # number of Writeback MSHR misses
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_mshrs no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_blocked_cycles_no_targets no value # average number of cycles each access was blocked
|
||||
system.cpu.l2cache.avg_refs 1.537705 # Average number of references to valid blocks.
|
||||
system.cpu.l2cache.blocked_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_mshrs 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.blocked_cycles_no_targets 0 # number of cycles access was blocked
|
||||
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
|
||||
system.cpu.l2cache.demand_accesses 276658 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3650.746755 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 108220 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 614924482 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.608831 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 168438 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_accesses 280779 # number of demand (read+write) accesses
|
||||
system.cpu.l2cache.demand_avg_miss_latency 3650.218185 # average overall miss latency
|
||||
system.cpu.l2cache.demand_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
|
||||
system.cpu.l2cache.demand_hits 112101 # number of demand (read+write) hits
|
||||
system.cpu.l2cache.demand_miss_latency 615711503 # number of demand (read+write) miss cycles
|
||||
system.cpu.l2cache.demand_miss_rate 0.600750 # miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_misses 168678 # number of demand (read+write) misses
|
||||
system.cpu.l2cache.demand_mshr_hits 0 # number of demand (read+write) MSHR hits
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 332289704 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.608831 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 168438 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.demand_mshr_miss_latency 332776620 # number of demand (read+write) MSHR miss cycles
|
||||
system.cpu.l2cache.demand_mshr_miss_rate 0.600750 # mshr miss rate for demand accesses
|
||||
system.cpu.l2cache.demand_mshr_misses 168678 # number of demand (read+write) MSHR misses
|
||||
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
|
||||
system.cpu.l2cache.mshr_cap_events 0 # number of times MSHR cap was activated
|
||||
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
||||
system.cpu.l2cache.overall_accesses 423793 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3638.111275 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.771607 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 254770 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 614924482 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.398834 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 169023 # number of overall misses
|
||||
system.cpu.l2cache.overall_accesses 428493 # number of overall (read+write) accesses
|
||||
system.cpu.l2cache.overall_avg_miss_latency 3640.764345 # average overall miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_miss_latency 1972.851350 # average overall mshr miss latency
|
||||
system.cpu.l2cache.overall_avg_mshr_uncacheable_latency no value # average overall mshr uncacheable latency
|
||||
system.cpu.l2cache.overall_hits 259377 # number of overall hits
|
||||
system.cpu.l2cache.overall_miss_latency 615711503 # number of overall miss cycles
|
||||
system.cpu.l2cache.overall_miss_rate 0.394676 # miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_misses 169116 # number of overall misses
|
||||
system.cpu.l2cache.overall_mshr_hits 0 # number of overall MSHR hits
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 332289704 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.397453 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 168438 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_miss_latency 332776620 # number of overall MSHR miss cycles
|
||||
system.cpu.l2cache.overall_mshr_miss_rate 0.393654 # mshr miss rate for overall accesses
|
||||
system.cpu.l2cache.overall_mshr_misses 168678 # number of overall MSHR misses
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_latency 0 # number of overall MSHR uncacheable cycles
|
||||
system.cpu.l2cache.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 # number of hwpf that were already in the cache
|
||||
|
|
@ -204,17 +204,17 @@ system.cpu.l2cache.prefetcher.num_hwpf_issued 0
|
|||
system.cpu.l2cache.prefetcher.num_hwpf_removed_MSHR_hit 0 # number of hwpf removed because MSHR allocated
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 # number of hwpf spanning a virtual page
|
||||
system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 # number of hwpf that got squashed due to a miss aborting calculation time
|
||||
system.cpu.l2cache.replacements 135670 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 168438 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.replacements 135910 # number of replacements
|
||||
system.cpu.l2cache.sampled_refs 168678 # Sample count of references to valid blocks.
|
||||
system.cpu.l2cache.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions
|
||||
system.cpu.l2cache.tagsinuse 30358.430189 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 254770 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 475381000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 115647 # number of writebacks
|
||||
system.cpu.l2cache.tagsinuse 30401.731729 # Cycle average of tags in use
|
||||
system.cpu.l2cache.total_refs 259377 # Total number of references to valid blocks.
|
||||
system.cpu.l2cache.warmup_cycle 667816000 # Cycle when the warmup percentage was hit.
|
||||
system.cpu.l2cache.writebacks 115911 # number of writebacks
|
||||
system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
|
||||
system.cpu.numCycles 1207510003 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88361899 # Number of instructions executed
|
||||
system.cpu.num_refs 35229376 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4706 # Number of system calls
|
||||
system.cpu.numCycles 1218558003 # number of cpu cycles simulated
|
||||
system.cpu.num_insts 88340674 # Number of instructions executed
|
||||
system.cpu.num_refs 35224019 # Number of memory references
|
||||
system.cpu.workload.PROG:num_syscalls 4583 # Number of system calls
|
||||
|
||||
---------- End Simulation Statistics ----------
|
||||
|
|
|
|||
|
|
@ -1 +1,2 @@
|
|||
0: system.remote_gdb.listener: listening for remote gdb on port 7000
|
||||
warn: Entering event queue @ 0. Starting simulation...
|
||||
|
|
|
|||
Loading…
Reference in a new issue