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ARM: Start over with translation from Alpha code as opposed to something that has cruft from 4 different ISAs.

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This commit is contained in:
Ali Saidi 2010-06-02 12:58:16 -05:00
parent 237c0617a0
commit 3aea20d143
5 changed files with 83 additions and 296 deletions
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1
src/arch/arm/SConscript
View file

@ -57,7 +57,6 @@ if env['TARGET_ISA'] == 'arm':
Source('insts/vfp.cc')
Source('miscregs.cc')
Source('nativetrace.cc')
Source('pagetable.cc')
Source('tlb.cc')
Source('vtophys.cc')
Source('utility.cc')

78
src/arch/arm/pagetable.cc
View file

@ -1,78 +0,0 @@
/*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Steve Reinhardt
* Jaidev Patwardhan
* Stephen Hines
*/
#include "arch/arm/pagetable.hh"
#include "sim/serialize.hh"
namespace ArmISA
{
void
PTE::serialize(std::ostream &os)
{
SERIALIZE_SCALAR(Mask);
SERIALIZE_SCALAR(VPN);
SERIALIZE_SCALAR(asid);
SERIALIZE_SCALAR(G);
SERIALIZE_SCALAR(PFN0);
SERIALIZE_SCALAR(D0);
SERIALIZE_SCALAR(V0);
SERIALIZE_SCALAR(C0);
SERIALIZE_SCALAR(PFN1);
SERIALIZE_SCALAR(D1);
SERIALIZE_SCALAR(V1);
SERIALIZE_SCALAR(C1);
SERIALIZE_SCALAR(AddrShiftAmount);
SERIALIZE_SCALAR(OffsetMask);
}
void
PTE::unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(Mask);
UNSERIALIZE_SCALAR(VPN);
UNSERIALIZE_SCALAR(asid);
UNSERIALIZE_SCALAR(G);
UNSERIALIZE_SCALAR(PFN0);
UNSERIALIZE_SCALAR(D0);
UNSERIALIZE_SCALAR(V0);
UNSERIALIZE_SCALAR(C0);
UNSERIALIZE_SCALAR(PFN1);
UNSERIALIZE_SCALAR(D1);
UNSERIALIZE_SCALAR(V1);
UNSERIALIZE_SCALAR(C1);
UNSERIALIZE_SCALAR(AddrShiftAmount);
UNSERIALIZE_SCALAR(OffsetMask);
}
}

109
src/arch/arm/pagetable.hh
View file

@ -1,7 +1,17 @@
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2002-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,8 +39,7 @@
*
* Authors: Nathan Binkert
* Steve Reinhardt
* Jaidev Patwardhan
* Stephen Hines
* Ali Saidi
*/
#ifndef __ARCH_ARM_PAGETABLE_H__
@ -43,59 +52,65 @@
namespace ArmISA {
struct VAddr
struct VAddr
{
VAddr(Addr a) { panic("not implemented yet."); }
};
// ITB/DTB page table entry
struct PTE
{
void serialize(std::ostream &os)
{
static const int ImplBits = 43;
static const Addr ImplMask = (ULL(1) << ImplBits) - 1;
static const Addr UnImplMask = ~ImplMask;
panic("Need to implement PTE serialization\n");
}
VAddr(Addr a) : addr(a) {}
Addr addr;
operator Addr() const { return addr; }
const VAddr &operator=(Addr a) { addr = a; return *this; }
Addr vpn() const { return (addr & ImplMask) >> PageShift; }
Addr page() const { return addr & Page_Mask; }
Addr offset() const { return addr & PageOffset; }
Addr level3() const
{ return ArmISA::PteAddr(addr >> PageShift); }
Addr level2() const
{ return ArmISA::PteAddr(addr >> (NPtePageShift + PageShift)); }
Addr level1() const
{ return ArmISA::PteAddr(addr >> (2 * NPtePageShift + PageShift)); }
};
// ITB/DTB page table entry
struct PTE
void unserialize(Checkpoint *cp, const std::string &section)
{
Addr Mask; // What parts of the VAddr (from bits 28..11) should be used in translation (includes Mask and MaskX from PageMask)
Addr VPN; // Virtual Page Number (/2) (Includes VPN2 + VPN2X .. bits 31..11 from EntryHi)
uint8_t asid; // Address Space ID (8 bits) // Lower 8 bits of EntryHi
panic("Need to implement PTE serialization\n");
}
bool G; // Global Bit - Obtained by an *AND* of EntryLo0 and EntryLo1 G bit
};
/* Contents of Entry Lo0 */
Addr PFN0; // Physical Frame Number - Even
bool D0; // Even entry Dirty Bit
bool V0; // Even entry Valid Bit
uint8_t C0; // Cache Coherency Bits - Even
// ITB/DTB table entry
struct TlbEntry
{
Addr tag; // virtual page number tag
Addr ppn; // physical page number
uint8_t asn; // address space number
bool valid; // valid page table entry
/* Contents of Entry Lo1 */
Addr PFN1; // Physical Frame Number - Odd
bool D1; // Odd entry Dirty Bit
bool V1; // Odd entry Valid Bit
uint8_t C1; // Cache Coherency Bits (3 bits)
/* The next few variables are put in as optimizations to reduce TLB lookup overheads */
/* For a given Mask, what is the address shift amount, and what is the OffsetMask */
int AddrShiftAmount;
int OffsetMask;
//Construct an entry that maps to physical address addr.
TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
{
tag = _vaddr >> PageShift;
ppn = _paddr >> PageShift;
asn = _asn;
valid = true;
}
TlbEntry()
{}
void
updateVaddr(Addr new_vaddr)
{
tag = new_vaddr >> PageShift;
}
Addr
pageStart()
{
return ppn << PageShift;
}
bool Valid() { return (V0 | V1);};
void serialize(std::ostream &os);
void unserialize(Checkpoint *cp, const std::string &section);
};
};
};
#endif // __ARCH_ARM_PAGETABLE_H__

127
src/arch/arm/tlb.cc
View file

@ -12,8 +12,6 @@
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -39,10 +37,9 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Authors: Ali Saidi
* Nathan Binkert
* Steve Reinhardt
* Jaidev Patwardhan
* Stephen Hines
*/
#include <string>
@ -64,19 +61,12 @@
using namespace std;
using namespace ArmISA;
///////////////////////////////////////////////////////////////////////
//
// ARM TLB
//
#define MODE2MASK(X) (1 << (X))
TLB::TLB(const Params *p)
: BaseTLB(p), size(p->size), nlu(0)
{
table = new ArmISA::PTE[size];
memset(table, 0, sizeof(ArmISA::PTE[size]));
smallPages=0;
}
TLB::~TLB()
@ -85,104 +75,10 @@ TLB::~TLB()
delete [] table;
}
// look up an entry in the TLB
ArmISA::PTE *
TLB::lookup(Addr vpn, uint8_t asn) const
{
// assume not found...
ArmISA::PTE *retval = NULL;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
while (i->first == vpn) {
int index = i->second;
ArmISA::PTE *pte = &table[index];
/* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
Addr Mask = pte->Mask;
Addr InvMask = ~Mask;
Addr VPN = pte->VPN;
// warn("Valid: %d - %d\n",pte->V0,pte->V1);
if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
{ // We have a VPN + ASID Match
retval = pte;
break;
}
++i;
}
}
DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
return retval;
}
ArmISA::PTE* TLB::getEntry(unsigned Index) const
{
// Make sure that Index is valid
assert(Index<size);
return &table[Index];
}
int TLB::probeEntry(Addr vpn,uint8_t asn) const
{
// assume not found...
ArmISA::PTE *retval = NULL;
int Ind=-1;
PageTable::const_iterator i = lookupTable.find(vpn);
if (i != lookupTable.end()) {
while (i->first == vpn) {
int index = i->second;
ArmISA::PTE *pte = &table[index];
/* 1KB TLB Lookup code - from ARM ARM Volume III - Rev. 2.50 */
Addr Mask = pte->Mask;
Addr InvMask = ~Mask;
Addr VPN = pte->VPN;
if(((vpn & InvMask) == (VPN & InvMask)) && (pte->G || (asn == pte->asid)))
{ // We have a VPN + ASID Match
retval = pte;
Ind = index;
break;
}
++i;
}
}
DPRINTF(Arm,"VPN: %x, asid: %d, Result of TLBP: %d\n",vpn,asn,Ind);
return Ind;
}
Fault inline
TLB::checkCacheability(RequestPtr &req)
{
Addr VAddrUncacheable = 0xA0000000;
// In ARM, cacheability is controlled by certain bits of the virtual address
// or by the TLB entry
if((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
// mark request as uncacheable
req->setFlags(Request::UNCACHEABLE);
}
return NoFault;
}
void TLB::insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages)
{
smallPages=_smallPages;
if(Index > size){
warn("Attempted to write at index (%d) beyond TLB size (%d)",Index,size);
} else {
// Update TLB
DPRINTF(TLB,"TLB[%d]: %x %x %x %x\n",Index,pte.Mask<<11,((pte.VPN << 11) | pte.asid),((pte.PFN0 <<6) | (pte.C0 << 3) | (pte.D0 << 2) | (pte.V0 <<1) | pte.G),
((pte.PFN1 <<6) | (pte.C1 << 3) | (pte.D1 << 2) | (pte.V1 <<1) | pte.G));
if(table[Index].V0 == true || table[Index].V1 == true){ // Previous entry is valid
PageTable::iterator i = lookupTable.find(table[Index].VPN);
lookupTable.erase(i);
}
table[Index]=pte;
// Update fast lookup table
lookupTable.insert(make_pair(table[Index].VPN, Index));
// int TestIndex=probeEntry(pte.VPN,pte.asid);
// warn("Inserted at: %d, Found at: %d (%x)\n",Index,TestIndex,pte.Mask);
}
panic("lookup() not implemented for ARM\n");
}
// insert a new TLB entry
@ -219,11 +115,9 @@ TLB::unserialize(Checkpoint *cp, const string &section)
UNSERIALIZE_SCALAR(size);
UNSERIALIZE_SCALAR(nlu);
panic("Need to properly unserialize TLB\n");
for (int i = 0; i < size; i++) {
table[i].unserialize(cp, csprintf("%s.PTE%d", section, i));
if (table[i].V0 || table[i].V1) {
lookupTable.insert(make_pair(table[i].VPN, i));
}
}
}
@ -334,17 +228,6 @@ TLB::translateTiming(RequestPtr req, ThreadContext *tc,
translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
}
ArmISA::PTE &
TLB::index(bool advance)
{
ArmISA::PTE *pte = &table[nlu];
if (advance)
nextnlu();
return *pte;
}
ArmISA::TLB *
ArmTLBParams::create()
{

60
src/arch/arm/tlb.hh
View file

@ -1,7 +1,17 @@
/*
* Copyright (c) 2010 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed hereunder. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Copyright (c) 2001-2005 The Regents of The University of Michigan
* Copyright (c) 2007 MIPS Technologies, Inc.
* Copyright (c) 2007-2008 The Florida State University
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -27,9 +37,7 @@
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Authors: Nathan Binkert
* Steve Reinhardt
* Stephen Hines
* Authors: Ali Saidi
*/
#ifndef __ARCH_ARM_TLB_HH__
@ -49,41 +57,8 @@
class ThreadContext;
/* ARM does not distinguish between a DTLB and an ITLB -> unified TLB
However, to maintain compatibility with other architectures, we'll
simply create an ITLB and DTLB that will point to the real TLB */
namespace ArmISA {
// WARN: This particular TLB entry is not necessarily conformed to ARM ISA
struct TlbEntry
{
Addr _pageStart;
TlbEntry() {}
TlbEntry(Addr asn, Addr vaddr, Addr paddr) : _pageStart(paddr) {}
void
updateVaddr(Addr new_vaddr)
{
panic("unimplemented");
}
Addr pageStart()
{
return _pageStart;
}
void serialize(std::ostream &os)
{
SERIALIZE_SCALAR(_pageStart);
}
void unserialize(Checkpoint *cp, const std::string &section)
{
UNSERIALIZE_SCALAR(_pageStart);
}
};
class TLB : public BaseTLB
{
public:
@ -112,6 +87,7 @@ class TLB : public BaseTLB
void nextnlu() { if (++nlu >= size) nlu = 0; }
ArmISA::PTE *lookup(Addr vpn, uint8_t asn) const;
// Access Stats
mutable Stats::Scalar read_hits;
mutable Stats::Scalar read_misses;
mutable Stats::Scalar read_acv;
@ -129,26 +105,18 @@ class TLB : public BaseTLB
typedef ArmTLBParams Params;
TLB(const Params *p);
int probeEntry(Addr vpn,uint8_t) const;
ArmISA::PTE *getEntry(unsigned) const;
virtual ~TLB();
int smallPages;
int getsize() const { return size; }
ArmISA::PTE &index(bool advance = true);
void insert(Addr vaddr, ArmISA::PTE &pte);
void insertAt(ArmISA::PTE &pte, unsigned Index, int _smallPages);
void flushAll();
void demapPage(Addr vaddr, uint64_t asn)
{
panic("demapPage unimplemented.\n");
}
// static helper functions... really
static bool validVirtualAddress(Addr vaddr);
static Fault checkCacheability(RequestPtr &req);
Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
void translateTiming(RequestPtr req, ThreadContext *tc,
Translation *translation, Mode mode);