Make CPU models use new LoadLockedReq/StoreCondReq commands.
--HG-- extra : convert_revision : ab78d9d1d88c3698edfd653d71c8882e1272b781
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5e59739416
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3ad761bc8e
6 changed files with 56 additions and 33 deletions
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@ -643,7 +643,10 @@ LSQUnit<Impl>::read(Request *req, T &data, int load_idx)
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// if we the cache is not blocked, do cache access
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if (!lsq->cacheBlocked()) {
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PacketPtr data_pkt =
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new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
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new Packet(req,
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(req->isLocked() ?
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MemCmd::LoadLockedReq : MemCmd::ReadReq),
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Packet::Broadcast);
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data_pkt->dataStatic(load_inst->memData);
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LSQSenderState *state = new LSQSenderState;
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@ -647,7 +647,9 @@ LSQUnit<Impl>::writebackStores()
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memcpy(inst->memData, storeQueue[storeWBIdx].data, req->getSize());
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MemCmd command = req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq;
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MemCmd command =
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req->isSwap() ? MemCmd::SwapReq :
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(req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
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PacketPtr data_pkt = new Packet(req, command,
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Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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@ -632,7 +632,11 @@ OzoneLWLSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
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DPRINTF(OzoneLSQ, "Doing timing access for inst PC %#x\n",
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inst->readPC());
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PacketPtr data_pkt = new Packet(req, Packet::ReadReq, Packet::Broadcast);
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PacketPtr data_pkt =
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new Packet(req,
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(req->isLocked() ?
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MemCmd::LoadLockedReq : Packet::ReadReq),
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Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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LSQSenderState *state = new LSQSenderState;
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@ -587,7 +587,10 @@ OzoneLWLSQ<Impl>::writebackStores()
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memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
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req->getSize());
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PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
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MemCmd command =
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req->isSwap() ? MemCmd::SwapReq :
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(req->isLocked() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
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PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
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data_pkt->dataStatic(inst->memData);
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LSQSenderState *state = new LSQSenderState;
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@ -280,7 +280,10 @@ AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
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// Now do the access.
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if (fault == NoFault) {
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Packet pkt = Packet(req, MemCmd::ReadReq, Packet::Broadcast);
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Packet pkt =
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Packet(req,
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req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
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Packet::Broadcast);
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pkt.dataStatic(&data);
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if (req->isMmapedIpr())
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@ -370,23 +373,24 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// Now do the access.
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if (fault == NoFault) {
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Packet pkt =
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Packet(req, req->isSwap() ? MemCmd::SwapReq : MemCmd::WriteReq,
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Packet::Broadcast);
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pkt.dataStatic(&data);
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MemCmd cmd = MemCmd::WriteReq; // default
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bool do_access = true; // flag to suppress cache access
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if (req->isLocked()) {
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cmd = MemCmd::StoreCondReq;
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do_access = TheISA::handleLockedWrite(thread, req);
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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}
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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if (do_access) {
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Packet pkt = Packet(req, cmd, Packet::Broadcast);
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pkt.dataStatic(&data);
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if (req->isMmapedIpr()) {
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dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
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} else {
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@ -395,12 +399,14 @@ AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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}
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dcache_access = true;
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assert(!pkt.isError());
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if (req->isSwap()) {
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assert(res);
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*res = pkt.get<T>();
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}
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}
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if (req->isSwap()) {
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assert(res);
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*res = pkt.get<T>();
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} else if (res) {
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if (res && !req->isSwap()) {
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*res = req->getExtraData();
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}
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}
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@ -260,7 +260,10 @@ TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
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// Now do the access.
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if (fault == NoFault) {
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PacketPtr pkt =
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new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
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new Packet(req,
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(req->isLocked() ?
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MemCmd::LoadLockedReq : MemCmd::ReadReq),
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Packet::Broadcast);
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pkt->dataDynamic<T>(new T);
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if (!dcachePort.sendTiming(pkt)) {
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@ -350,25 +353,27 @@ TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
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// Now do the access.
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if (fault == NoFault) {
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assert(dcache_pkt == NULL);
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if (req->isSwap())
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dcache_pkt = new Packet(req, MemCmd::SwapReq, Packet::Broadcast);
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else
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dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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MemCmd cmd = MemCmd::WriteReq; // default
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bool do_access = true; // flag to suppress cache access
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assert(dcache_pkt == NULL);
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if (req->isLocked()) {
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cmd = MemCmd::StoreCondReq;
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do_access = TheISA::handleLockedWrite(thread, req);
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}
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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} else if (req->isSwap()) {
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cmd = MemCmd::SwapReq;
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if (req->isCondSwap()) {
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assert(res);
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req->setExtraData(*res);
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}
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}
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if (do_access) {
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dcache_pkt = new Packet(req, MemCmd::WriteReq, Packet::Broadcast);
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dcache_pkt->allocate();
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dcache_pkt->set(data);
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if (!dcachePort.sendTiming(dcache_pkt)) {
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_status = DcacheRetry;
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} else {
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@ -609,7 +614,7 @@ TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
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Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
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if (pkt->isRead() && pkt->req->isLocked()) {
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if (pkt->isRead() && pkt->isLocked()) {
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TheISA::handleLockedRead(thread, pkt->req);
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}
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