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ARM: Ignore/warn on accesses to the BPIALLIS and BPIALL registers.

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This commit is contained in:
Gabe Black 2010-06-02 12:58:10 -05:00
parent faf6c727f6
commit 3aa8faf177
2 changed files with 12 additions and 5 deletions
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6
src/arch/arm/isa/formats/misc.isa
View file

@ -122,6 +122,12 @@ def format McrMrc15() {{
case MISCREG_BPIMVA: case MISCREG_BPIMVA:
return new WarnUnimplemented( return new WarnUnimplemented(
isRead ? "mrc bpimva" : "mcr bpimva", machInst); isRead ? "mrc bpimva" : "mcr bpimva", machInst);
case MISCREG_BPIALLIS:
return new WarnUnimplemented(
isRead ? "mrc bpiallis" : "mcr bpiallis", machInst);
case MISCREG_BPIALL:
return new WarnUnimplemented(
isRead ? "mrc bpiall" : "mcr bpiall", machInst);
default: default:
if (isRead) { if (isRead) {
return new Mrc15(machInst, rt, (IntRegIndex)miscReg); return new Mrc15(machInst, rt, (IntRegIndex)miscReg);

11
src/arch/arm/miscregs.hh
View file

@ -100,6 +100,8 @@ namespace ArmISA
MISCREG_ICIALLU, MISCREG_ICIALLU,
MISCREG_ICIMVAU, MISCREG_ICIMVAU,
MISCREG_BPIMVA, MISCREG_BPIMVA,
MISCREG_BPIALLIS,
MISCREG_BPIALL,
MISCREG_CP15_UNIMP_START, MISCREG_CP15_UNIMP_START,
MISCREG_CTR = MISCREG_CP15_UNIMP_START, MISCREG_CTR = MISCREG_CP15_UNIMP_START,
MISCREG_TCMTR, MISCREG_TCMTR,
@ -135,8 +137,6 @@ namespace ArmISA
MISCREG_DRACR, MISCREG_DRACR,
MISCREG_IRACR, MISCREG_IRACR,
MISCREG_RGNR, MISCREG_RGNR,
MISCREG_BPIALLIS,
MISCREG_BPIALL,
MISCREG_DCIMVAC, MISCREG_DCIMVAC,
MISCREG_DCISW, MISCREG_DCISW,
MISCREG_MCCSW, MISCREG_MCCSW,
@ -162,7 +162,8 @@ namespace ArmISA
"contextidr", "tpidrurw", "tpidruro", "tpidrprw", "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
"cp15isb", "cp15dsb", "cp15dmb", "cpacr", "cp15isb", "cp15dsb", "cp15dmb", "cpacr",
"clidr", "ccsidr", "csselr", "clidr", "ccsidr", "csselr",
"icialluis", "iciallu", "icimvau", "bpimva", "icialluis", "iciallu", "icimvau",
"bpimva", "bpiallis", "bpiall",
"ctr", "tcmtr", "mpuir", "mpidr", "midr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
"id_pfr0", "id_pfr1", "id_dfr0", "id_afr0", "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
"id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3", "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
@ -170,8 +171,8 @@ namespace ArmISA
"aidr", "actlr", "aidr", "actlr",
"dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar", "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
"drbar", "irbar", "drsr", "irsr", "dracr", "iracr", "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
"rgnr", "bpiallis", "rgnr",
"bpiall", "dcimvac", "dcisw", "mccsw", "dcimvac", "dcisw", "mccsw",
"dccmvau", "dccmvau",
"nop", "raz" "nop", "raz"
}; };