X86: Create a mechanism for the IO APIC to access I8259 vectors.
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c35da8e495
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5 changed files with 97 additions and 28 deletions
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@ -30,12 +30,13 @@
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#include "arch/x86/intmessage.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8259.hh"
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#include "mem/packet.hh"
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#include "mem/packet_access.hh"
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#include "sim/system.hh"
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X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this),
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latency(p->pio_latency), pioAddr(p->pio_addr)
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latency(p->pio_latency), pioAddr(p->pio_addr), extIntPic(NULL)
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{
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// This assumes there's only one I/O APIC in the system
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id = sys->getNumCPUs();
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@ -145,25 +146,28 @@ X86ISA::I82094AA::signalInterrupt(int line)
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DPRINTF(I82094AA, "Entry was masked.\n");
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return;
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} else {
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if (DTRACE(I82094AA)) {
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if (DeliveryMode::isReserved(entry.deliveryMode)) {
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fatal("Tried to use reserved delivery mode "
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"for IO APIC entry %d.\n", line);
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} else {
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DPRINTF(I82094AA, "Delivery mode is: %s.\n",
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DeliveryMode::names[entry.deliveryMode]);
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}
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DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector);
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}
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TriggerIntMessage message;
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message.destination = entry.dest;
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if (entry.deliveryMode == DeliveryMode::ExtInt) {
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assert(extIntPic);
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message.vector = extIntPic->getVector();
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} else {
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message.vector = entry.vector;
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}
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message.deliveryMode = entry.deliveryMode;
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message.destMode = entry.destMode;
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message.level = entry.polarity;
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message.trigger = entry.trigger;
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if (DeliveryMode::isReserved(entry.deliveryMode)) {
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fatal("Tried to use reserved delivery mode "
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"for IO APIC entry %d.\n", line);
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} else if (DTRACE(I82094AA)) {
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DPRINTF(I82094AA, "Delivery mode is: %s.\n",
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DeliveryMode::names[entry.deliveryMode]);
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DPRINTF(I82094AA, "Vector is %#x.\n", message.vector);
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}
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if (entry.destMode == 0) {
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DPRINTF(I82094AA,
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"Sending interrupt to APIC ID %d.\n", entry.dest);
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@ -40,6 +40,8 @@
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namespace X86ISA
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{
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class I8259;
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class I82094AA : public PioDevice, public IntDev
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{
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public:
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@ -60,10 +62,11 @@ class I82094AA : public PioDevice, public IntDev
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EndBitUnion(RedirTableEntry)
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protected:
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System * system;
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Tick latency;
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Addr pioAddr;
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I8259 * extIntPic;
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uint8_t regSel;
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uint8_t id;
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uint8_t arbId;
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@ -86,6 +89,12 @@ class I82094AA : public PioDevice, public IntDev
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I82094AA(Params *p);
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void
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setExtIntPic(I8259 * pic)
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{
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extIntPic = pic;
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}
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Tick read(PacketPtr pkt);
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Tick write(PacketPtr pkt);
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@ -29,8 +29,28 @@
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*/
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#include "base/bitfield.hh"
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#include "dev/x86/i82094aa.hh"
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#include "dev/x86/i8259.hh"
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X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
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latency(p->pio_latency), output(p->output),
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mode(p->mode), slave(NULL),
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IRR(0), ISR(0), IMR(0),
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readIRR(true), initControlWord(0)
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{
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if (output) {
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I8259 * master;
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master = dynamic_cast<I8259 *>(output->getDevice());
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if (master)
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master->setSlave(this);
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I82094AA * ioApic;
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ioApic = dynamic_cast<I82094AA *>(output->getDevice());
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if (ioApic)
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ioApic->setExtIntPic(this);
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}
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pioSize = 2;
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}
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Tick
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X86ISA::I8259::read(PacketPtr pkt)
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{
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@ -189,11 +209,14 @@ void
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X86ISA::I8259::signalInterrupt(int line)
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{
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DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
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if (line > 7)
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fatal("Line number %d doesn't exist. The max is 7.\n");
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if (line >= NumLines)
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fatal("Line number %d doesn't exist. The max is %d.\n",
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line, NumLines - 1);
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if (bits(IMR, line)) {
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DPRINTF(I8259, "Interrupt %d was masked.\n", line);
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} else {
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IRR |= 1 << line;
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if (bits(ISR, 7, line) == 0) {
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if (output) {
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DPRINTF(I8259, "Propogating interrupt.\n");
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output->signalInterrupt();
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@ -203,6 +226,28 @@ X86ISA::I8259::signalInterrupt(int line)
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}
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}
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}
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}
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int
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X86ISA::I8259::getVector()
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{
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/*
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* This code only handles one slave. Since that's how the PC platform
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* always uses the 8259 PIC, there shouldn't be any need for more. If
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* there -is- a need for more for some reason, "slave" can become a
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* vector of slaves.
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*/
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int line = findMsbSet(IRR);
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IRR &= ~(1 << line);
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DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
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ISR |= 1 << line;
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if (slave && bits(cascadeBits, line)) {
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DPRINTF(I8259, "Interrupt was from slave who will "
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"provide the vector.\n");
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return slave->getVector();
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}
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return line | vectorOffset;
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}
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X86ISA::I8259 *
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I8259Params::create()
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@ -39,12 +39,17 @@
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namespace X86ISA
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{
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class I82094AA;
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class I8259 : public BasicPioDevice, public IntDev
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{
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protected:
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static const int NumLines = 8;
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Tick latency;
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IntPin *output;
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Enums::X86I8259CascadeMode mode;
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I8259 * slave;
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// Interrupt Request Register
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uint8_t IRR;
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@ -77,19 +82,19 @@ class I8259 : public BasicPioDevice, public IntDev
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return dynamic_cast<const Params *>(_params);
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}
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I8259(Params * p) : BasicPioDevice(p), IntDev(this),
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latency(p->pio_latency), output(p->output),
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mode(p->mode), IRR(0), ISR(0), IMR(0),
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vectorOffset(0), readIRR(true), initControlWord(0)
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I8259(Params * p);
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void
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setSlave(I8259 * _slave)
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{
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pioSize = 2;
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slave = _slave;
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}
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Tick read(PacketPtr pkt);
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Tick write(PacketPtr pkt);
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void signalInterrupt(int line);
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int getVector();
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};
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}; // namespace X86ISA
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@ -122,6 +122,12 @@ class IntPin : public SimObject
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public:
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typedef X86IntPinParams Params;
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IntDev *
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getDevice() const
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{
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return device;
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}
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const Params *
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params() const
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{
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