ruby: Fix block_on behavior
Ruby's controller block_on behavior aimed to block MessageBuffer requests into SLICC controllers when a Locked_RMW was in flight. Unfortunately, this functionality only partially works: When non-Locked_RMW memory accesses are issued to the sequencer to an address with an in-flight Locked_RMW, the sequencer may pass those accesses through to the controller. At the controller, a number of incorrect activities can occur depending on the protocol. In MOESI_hammer, for example, an intermediate IFETCH will cause an L1D to L2 transfer, which cannot be serviced, because the block_on functionality blocks the trigger queue, resulting in a deadlock. Further, if an intermediate store arrives (e.g. from a separate SMT thread), the sequencer allows the request through to the controller, and the atomicity of the Locked_RMW may be broken. To avoid these problems, disallow the Sequencer from passing any memory accesses to the controller besides Locked_RMW_Write when a Locked_RMW is in- flight.
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3 changed files with 25 additions and 0 deletions
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@ -192,6 +192,12 @@ AbstractController::blockOnQueue(Addr addr, MessageBuffer* port)
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m_block_map[addr] = port;
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m_block_map[addr] = port;
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}
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}
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bool
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AbstractController::isBlocked(Addr addr) const
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{
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return m_is_blocking && (m_block_map.find(addr) != m_block_map.end());
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}
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void
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void
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AbstractController::unblock(Addr addr)
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AbstractController::unblock(Addr addr)
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{
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{
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@ -73,6 +73,7 @@ class AbstractController : public MemObject, public Consumer
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// return instance name
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// return instance name
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void blockOnQueue(Addr, MessageBuffer*);
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void blockOnQueue(Addr, MessageBuffer*);
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bool isBlocked(Addr) const;
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void unblock(Addr);
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void unblock(Addr);
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bool isBlocked(Addr);
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bool isBlocked(Addr);
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@ -173,6 +173,16 @@ Sequencer::insertRequest(PacketPtr pkt, RubyRequestType request_type)
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}
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}
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Addr line_addr = makeLineAddress(pkt->getAddr());
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Addr line_addr = makeLineAddress(pkt->getAddr());
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// Check if the line is blocked for a Locked_RMW
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if (m_controller->isBlocked(line_addr) &&
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(request_type != RubyRequestType_Locked_RMW_Write)) {
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// Return that this request's cache line address aliases with
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// a prior request that locked the cache line. The request cannot
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// proceed until the cache line is unlocked by a Locked_RMW_Write
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return RequestStatus_Aliased;
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}
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// Create a default entry, mapping the address to NULL, the cast is
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// Create a default entry, mapping the address to NULL, the cast is
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// there to make gcc 4.4 happy
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// there to make gcc 4.4 happy
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RequestTable::value_type default_entry(line_addr,
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RequestTable::value_type default_entry(line_addr,
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@ -382,7 +392,15 @@ Sequencer::writeCallback(Addr address, DataBlock& data,
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if (!m_usingNetworkTester)
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if (!m_usingNetworkTester)
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success = handleLlsc(address, request);
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success = handleLlsc(address, request);
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// Handle SLICC block_on behavior for Locked_RMW accesses. NOTE: the
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// address variable here is assumed to be a line address, so when
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// blocking buffers, must check line addresses.
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if (request->m_type == RubyRequestType_Locked_RMW_Read) {
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if (request->m_type == RubyRequestType_Locked_RMW_Read) {
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// blockOnQueue blocks all first-level cache controller queues
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// waiting on memory accesses for the specified address that go to
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// the specified queue. In this case, a Locked_RMW_Write must go to
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// the mandatory_q before unblocking the first-level controller.
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// This will block standard loads, stores, ifetches, etc.
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m_controller->blockOnQueue(address, m_mandatory_q_ptr);
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m_controller->blockOnQueue(address, m_mandatory_q_ptr);
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} else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
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} else if (request->m_type == RubyRequestType_Locked_RMW_Write) {
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m_controller->unblock(address);
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m_controller->unblock(address);
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