sanchayanmaity/gem5
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

Always get the functional access from the highest level of cache first.

Browse source 
src/mem/cache/cache_impl.hh:
    Get the read data from the highest level of cache on a functional access

--HG--
extra : convert_revision : 7437ac46fb40f3ea3b42197a1aa8aec62af60181
This commit is contained in:
Ron Dreslinski 2006-10-19 19:00:27 -04:00
parent 5bcdc74fe2
commit 39d24f7241
1 changed files with 115 additions and 116 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

21
src/mem/cache/cache_impl.hh vendored
View file

@ -536,6 +536,13 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
}
}
if (!update && (pkt->isWrite() || (otherSidePort == cpuSidePort))) {
// Still need to change data in all locations.
otherSidePort->sendFunctional(pkt);
if (pkt->isRead() && pkt->result == Packet::Success)
return 0;
}
PacketList writebacks;
int lat;
BlkType *blk = tags->handleAccess(pkt, lat, writebacks, update);
@ -544,7 +551,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
pkt->getAddr() & (((ULL(1))<<48)-1), (blk) ? "hit" : "miss",
pkt->getAddr() & ~((Addr)blkSize - 1));
if (!blk) {
// Need to check for outstanding misses and writes
Addr blk_addr = pkt->getAddr() & ~(blkSize - 1);
@ -556,8 +563,6 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
missQueue->findWrites(blk_addr, writes);
if (!update) {
otherSidePort->sendFunctional(pkt);
// Check for data in MSHR and writebuffer.
if (mshr) {
warn("Found outstanding miss on an non-update probe");
@ -631,8 +636,7 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
}
}
return 0;
} else {
} else if (!blk) {
// update the cache state and statistics
if (mshr || !writes.empty()){
// Can't handle it, return pktuest unsatisfied.
@ -699,7 +703,6 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
} else {
return memSidePort->sendAtomic(pkt);
}
}
} else {
// There was a cache hit.
// Handle writebacks if needed
@ -708,12 +711,8 @@ Cache<TagStore,Buffering,Coherence>::probe(Packet * &pkt, bool update,
writebacks.pop_front();
}
if (update) {
hits[pkt->cmdToIndex()][0/*pkt->req->getThreadNum()*/]++;
} else if (pkt->isWrite()) {
// Still need to change data in all locations.
otherSidePort->sendFunctional(pkt);
}
return hitLatency;
}
fatal("Probe not handled.\n");