Changed name of lisa's device to NSgigE instead of Etherdev so it
doesn't conflict with the old ethernet driver name.
Added config file to try to boot Tru64 with Tsunami
Cleaned up kern/linux a bit more and fixed bug where we were using
Tru64 system calls
dev/ns_gige.cc:
dev/ns_gige.hh:
dev/tsunami.hh:
Changed name of lisa's device to NSgigE instead of Etherdev so it
doesn't conflict with the old ethernet driver name.
kern/linux/linux_syscalls.hh:
the Syscalls still used the Tru64 calls, oops.. fixed.
--HG--
extra : convert_revision : dedd20686cc367ed37f31920f753566afbc69045
This commit is contained in:
Ali Saidi
parent
74c494a4eb
commit
391f228fda
4 changed files with 84 additions and 82 deletions
118
dev/ns_gige.cc
118
dev/ns_gige.cc
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@ -88,9 +88,9 @@ using namespace std;
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///////////////////////////////////////////////////////////////////////
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//
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// EtherDev PCI Device
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// NSGigE PCI Device
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//
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EtherDev::EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
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NSGigE::NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
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PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
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MemoryController *mmu, HierParams *hier, Bus *header_bus,
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Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
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@ -120,7 +120,7 @@ EtherDev::EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
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if (header_bus) {
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pioInterface = newPioInterface(name, hier, header_bus, this,
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&EtherDev::cacheAccess);
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&NSGigE::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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if (payload_bus)
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dmaInterface = new DMAInterface<Bus>(name + ".dma",
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@ -130,7 +130,7 @@ EtherDev::EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
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header_bus, header_bus, 1);
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} else if (payload_bus) {
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pioInterface = newPioInterface(name, hier, payload_bus, this,
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&EtherDev::cacheAccess);
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&NSGigE::cacheAccess);
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pioInterface->addAddrRange(addr, addr + size - 1);
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dmaInterface = new DMAInterface<Bus>(name + ".dma",
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payload_bus, payload_bus, 1);
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@ -154,11 +154,11 @@ EtherDev::EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
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rom.perfectMatch[5] = eaddr[5];
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}
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EtherDev::~EtherDev()
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NSGigE::~NSGigE()
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{}
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void
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EtherDev::regStats()
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NSGigE::regStats()
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{
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txBytes
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.name(name() + ".txBytes")
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@ -222,7 +222,7 @@ EtherDev::regStats()
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* This is to read the PCI general configuration registers
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*/
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void
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EtherDev::ReadConfig(int offset, int size, uint8_t *data)
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NSGigE::ReadConfig(int offset, int size, uint8_t *data)
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{
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if (offset < PCI_DEVICE_SPECIFIC)
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PciDev::ReadConfig(offset, size, data);
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@ -235,7 +235,7 @@ EtherDev::ReadConfig(int offset, int size, uint8_t *data)
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* This is to write to the PCI general configuration registers
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*/
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void
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EtherDev::WriteConfig(int offset, int size, uint32_t data)
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NSGigE::WriteConfig(int offset, int size, uint32_t data)
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{
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if (offset < PCI_DEVICE_SPECIFIC)
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PciDev::WriteConfig(offset, size, data);
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@ -248,7 +248,7 @@ EtherDev::WriteConfig(int offset, int size, uint32_t data)
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* spec sheet
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*/
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Fault
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EtherDev::read(MemReqPtr &req, uint8_t *data)
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NSGigE::read(MemReqPtr &req, uint8_t *data)
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{
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//The mask is to give you only the offset into the device register file
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Addr daddr = req->paddr & 0xfff;
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@ -450,7 +450,7 @@ EtherDev::read(MemReqPtr &req, uint8_t *data)
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}
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Fault
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EtherDev::write(MemReqPtr &req, const uint8_t *data)
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NSGigE::write(MemReqPtr &req, const uint8_t *data)
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{
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Addr daddr = req->paddr & 0xfff;
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DPRINTF(EthernetPIO, "write da=%#x pa=%#x va=%#x size=%d\n",
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@ -791,7 +791,7 @@ EtherDev::write(MemReqPtr &req, const uint8_t *data)
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}
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void
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EtherDev::devIntrPost(uint32_t interrupts)
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NSGigE::devIntrPost(uint32_t interrupts)
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{
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DPRINTF(Ethernet, "interrupt posted intr=%#x isr=%#x imr=%#x\n",
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interrupts, regs.isr, regs.imr);
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@ -860,7 +860,7 @@ EtherDev::devIntrPost(uint32_t interrupts)
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}
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void
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EtherDev::devIntrClear(uint32_t interrupts)
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NSGigE::devIntrClear(uint32_t interrupts)
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{
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DPRINTF(Ethernet, "interrupt cleared intr=%x isr=%x imr=%x\n",
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interrupts, regs.isr, regs.imr);
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@ -919,7 +919,7 @@ EtherDev::devIntrClear(uint32_t interrupts)
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}
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void
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EtherDev::devIntrChangeMask()
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NSGigE::devIntrChangeMask()
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{
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DPRINTF(Ethernet, "interrupt mask changed\n");
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@ -930,7 +930,7 @@ EtherDev::devIntrChangeMask()
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}
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void
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EtherDev::cpuIntrPost(Tick when)
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NSGigE::cpuIntrPost(Tick when)
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{
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if (when > intrTick && intrTick != 0)
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return;
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@ -951,7 +951,7 @@ EtherDev::cpuIntrPost(Tick when)
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}
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void
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EtherDev::cpuInterrupt()
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NSGigE::cpuInterrupt()
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{
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// Don't send an interrupt if there's already one
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if (cpuPendingIntr)
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@ -974,7 +974,7 @@ EtherDev::cpuInterrupt()
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}
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void
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EtherDev::cpuIntrClear()
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NSGigE::cpuIntrClear()
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{
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if (cpuPendingIntr) {
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cpuPendingIntr = false;
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@ -985,11 +985,11 @@ EtherDev::cpuIntrClear()
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}
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bool
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EtherDev::cpuIntrPending() const
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NSGigE::cpuIntrPending() const
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{ return cpuPendingIntr; }
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void
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EtherDev::txReset()
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NSGigE::txReset()
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{
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DPRINTF(Ethernet, "transmit reset\n");
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@ -1007,7 +1007,7 @@ EtherDev::txReset()
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}
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void
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EtherDev::rxReset()
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NSGigE::rxReset()
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{
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DPRINTF(Ethernet, "receive reset\n");
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@ -1024,7 +1024,7 @@ EtherDev::rxReset()
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}
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void
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EtherDev::rxDmaReadCopy()
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NSGigE::rxDmaReadCopy()
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{
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assert(rxDmaState == dmaReading);
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@ -1037,7 +1037,7 @@ EtherDev::rxDmaReadCopy()
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}
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bool
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EtherDev::doRxDmaRead()
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NSGigE::doRxDmaRead()
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{
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assert(rxDmaState == dmaIdle || rxDmaState == dmaReadWaiting);
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rxDmaState = dmaReading;
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@ -1063,7 +1063,7 @@ EtherDev::doRxDmaRead()
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}
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void
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EtherDev::rxDmaReadDone()
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NSGigE::rxDmaReadDone()
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{
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assert(rxDmaState == dmaReading);
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rxDmaReadCopy();
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@ -1076,7 +1076,7 @@ EtherDev::rxDmaReadDone()
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}
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void
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EtherDev::rxDmaWriteCopy()
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NSGigE::rxDmaWriteCopy()
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{
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assert(rxDmaState == dmaWriting);
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@ -1089,7 +1089,7 @@ EtherDev::rxDmaWriteCopy()
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}
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bool
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EtherDev::doRxDmaWrite()
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NSGigE::doRxDmaWrite()
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{
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assert(rxDmaState == dmaIdle || rxDmaState == dmaWriteWaiting);
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rxDmaState = dmaWriting;
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@ -1115,7 +1115,7 @@ EtherDev::doRxDmaWrite()
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}
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void
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EtherDev::rxDmaWriteDone()
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NSGigE::rxDmaWriteDone()
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{
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assert(rxDmaState == dmaWriting);
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rxDmaWriteCopy();
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@ -1128,7 +1128,7 @@ EtherDev::rxDmaWriteDone()
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}
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void
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EtherDev::rxKick()
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NSGigE::rxKick()
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{
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DPRINTF(Ethernet, "receive kick state=%s (rxBuf.size=%d)\n",
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NsRxStateStrings[rxState], rxFifo.size());
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@ -1388,7 +1388,7 @@ EtherDev::rxKick()
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}
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void
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EtherDev::transmit()
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NSGigE::transmit()
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{
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if (txFifo.empty()) {
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DPRINTF(Ethernet, "nothing to transmit\n");
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@ -1421,7 +1421,7 @@ EtherDev::transmit()
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}
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void
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EtherDev::txDmaReadCopy()
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NSGigE::txDmaReadCopy()
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{
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assert(txDmaState == dmaReading);
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@ -1434,7 +1434,7 @@ EtherDev::txDmaReadCopy()
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}
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bool
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EtherDev::doTxDmaRead()
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NSGigE::doTxDmaRead()
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{
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assert(txDmaState == dmaIdle || txDmaState == dmaReadWaiting);
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txDmaState = dmaReading;
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@ -1460,7 +1460,7 @@ EtherDev::doTxDmaRead()
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}
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void
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EtherDev::txDmaReadDone()
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NSGigE::txDmaReadDone()
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{
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assert(txDmaState == dmaReading);
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txDmaReadCopy();
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@ -1473,7 +1473,7 @@ EtherDev::txDmaReadDone()
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}
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void
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EtherDev::txDmaWriteCopy()
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NSGigE::txDmaWriteCopy()
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{
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assert(txDmaState == dmaWriting);
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@ -1486,7 +1486,7 @@ EtherDev::txDmaWriteCopy()
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}
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bool
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EtherDev::doTxDmaWrite()
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NSGigE::doTxDmaWrite()
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{
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assert(txDmaState == dmaIdle || txDmaState == dmaWriteWaiting);
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txDmaState = dmaWriting;
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@ -1512,7 +1512,7 @@ EtherDev::doTxDmaWrite()
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}
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void
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EtherDev::txDmaWriteDone()
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NSGigE::txDmaWriteDone()
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{
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assert(txDmaState == dmaWriting);
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txDmaWriteCopy();
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@ -1525,7 +1525,7 @@ EtherDev::txDmaWriteDone()
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}
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void
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EtherDev::txKick()
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NSGigE::txKick()
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{
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DPRINTF(Ethernet, "transmit kick state=%s\n", NsTxStateStrings[txState]);
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@ -1777,7 +1777,7 @@ EtherDev::txKick()
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}
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void
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EtherDev::transferDone()
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NSGigE::transferDone()
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{
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if (txFifo.empty())
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return;
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@ -1791,7 +1791,7 @@ EtherDev::transferDone()
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}
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bool
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EtherDev::rxFilter(PacketPtr packet)
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NSGigE::rxFilter(PacketPtr packet)
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{
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bool drop = true;
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string type;
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@ -1841,7 +1841,7 @@ EtherDev::rxFilter(PacketPtr packet)
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}
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bool
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EtherDev::recvPacket(PacketPtr packet)
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NSGigE::recvPacket(PacketPtr packet)
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{
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rxBytes += packet->length;
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rxPackets++;
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@ -1878,7 +1878,7 @@ EtherDev::recvPacket(PacketPtr packet)
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* else, it just checks what it calculates against the value in the header in packet
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*/
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bool
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EtherDev::udpChecksum(PacketPtr packet, bool gen)
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NSGigE::udpChecksum(PacketPtr packet, bool gen)
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{
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udp_header *hdr = (udp_header *) packet->getTransportHdr();
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@ -1905,7 +1905,7 @@ EtherDev::udpChecksum(PacketPtr packet, bool gen)
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}
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bool
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EtherDev::tcpChecksum(PacketPtr packet, bool gen)
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NSGigE::tcpChecksum(PacketPtr packet, bool gen)
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{
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tcp_header *hdr = (tcp_header *) packet->getTransportHdr();
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@ -1932,7 +1932,7 @@ EtherDev::tcpChecksum(PacketPtr packet, bool gen)
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}
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bool
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EtherDev::ipChecksum(PacketPtr packet, bool gen)
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NSGigE::ipChecksum(PacketPtr packet, bool gen)
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{
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ip_header *hdr = packet->getIpHdr();
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@ -1948,7 +1948,7 @@ EtherDev::ipChecksum(PacketPtr packet, bool gen)
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}
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uint16_t
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EtherDev::checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len)
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NSGigE::checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len)
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{
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uint32_t sum = 0;
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@ -1978,7 +1978,7 @@ EtherDev::checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len)
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//
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//
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void
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EtherDev::serialize(ostream &os)
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NSGigE::serialize(ostream &os)
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{
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/*
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* Finalize any DMA events now.
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@ -2129,7 +2129,7 @@ EtherDev::serialize(ostream &os)
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}
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void
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EtherDev::unserialize(Checkpoint *cp, const std::string §ion)
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NSGigE::unserialize(Checkpoint *cp, const std::string §ion)
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{
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UNSERIALIZE_SCALAR(regs.command);
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UNSERIALIZE_SCALAR(regs.config);
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@ -2277,7 +2277,7 @@ EtherDev::unserialize(Checkpoint *cp, const std::string §ion)
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Tick
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EtherDev::cacheAccess(MemReqPtr &req)
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NSGigE::cacheAccess(MemReqPtr &req)
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{
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DPRINTF(EthernetPIO, "timing access to paddr=%#x (daddr=%#x)\n",
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req->paddr, req->paddr - addr);
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@ -2286,23 +2286,23 @@ EtherDev::cacheAccess(MemReqPtr &req)
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//=====================================================================
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDevInt)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
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SimObjectParam<EtherInt *> peer;
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SimObjectParam<EtherDev *> device;
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SimObjectParam<NSGigE *> device;
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END_DECLARE_SIM_OBJECT_PARAMS(EtherDevInt)
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END_DECLARE_SIM_OBJECT_PARAMS(NSGigEInt)
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BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDevInt)
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BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
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INIT_PARAM_DFLT(peer, "peer interface", NULL),
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INIT_PARAM(device, "Ethernet device of this interface")
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END_INIT_SIM_OBJECT_PARAMS(EtherDevInt)
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END_INIT_SIM_OBJECT_PARAMS(NSGigEInt)
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CREATE_SIM_OBJECT(EtherDevInt)
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CREATE_SIM_OBJECT(NSGigEInt)
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{
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EtherDevInt *dev_int = new EtherDevInt(getInstanceName(), device);
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NSGigEInt *dev_int = new NSGigEInt(getInstanceName(), device);
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EtherInt *p = (EtherInt *)peer;
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if (p) {
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@ -2313,10 +2313,10 @@ CREATE_SIM_OBJECT(EtherDevInt)
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return dev_int;
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}
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REGISTER_SIM_OBJECT("EtherDevInt", EtherDevInt)
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REGISTER_SIM_OBJECT("NSGigEInt", NSGigEInt)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDev)
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BEGIN_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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Param<Tick> tx_delay;
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Param<Tick> rx_delay;
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@ -2344,9 +2344,9 @@ BEGIN_DECLARE_SIM_OBJECT_PARAMS(EtherDev)
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Param<uint32_t> pci_dev;
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Param<uint32_t> pci_func;
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END_DECLARE_SIM_OBJECT_PARAMS(EtherDev)
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END_DECLARE_SIM_OBJECT_PARAMS(NSGigE)
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BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDev)
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BEGIN_INIT_SIM_OBJECT_PARAMS(NSGigE)
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INIT_PARAM_DFLT(tx_delay, "Transmit Delay", 1000),
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INIT_PARAM_DFLT(rx_delay, "Receive Delay", 1000),
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@ -2375,16 +2375,16 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(EtherDev)
|
|||
INIT_PARAM(pci_dev, "PCI device number"),
|
||||
INIT_PARAM(pci_func, "PCI function code")
|
||||
|
||||
END_INIT_SIM_OBJECT_PARAMS(EtherDev)
|
||||
END_INIT_SIM_OBJECT_PARAMS(NSGigE)
|
||||
|
||||
|
||||
CREATE_SIM_OBJECT(EtherDev)
|
||||
CREATE_SIM_OBJECT(NSGigE)
|
||||
{
|
||||
int eaddr[6];
|
||||
sscanf(((string)hardware_address).c_str(), "%x:%x:%x:%x:%x:%x",
|
||||
&eaddr[0], &eaddr[1], &eaddr[2], &eaddr[3], &eaddr[4], &eaddr[5]);
|
||||
|
||||
return new EtherDev(getInstanceName(), intr_ctrl, intr_delay,
|
||||
return new NSGigE(getInstanceName(), intr_ctrl, intr_delay,
|
||||
physmem, tx_delay, rx_delay, mmu, hier, header_bus,
|
||||
payload_bus, pio_latency, dma_desc_free, dma_data_free,
|
||||
dma_read_delay, dma_write_delay, dma_read_factor,
|
||||
|
|
@ -2393,4 +2393,4 @@ CREATE_SIM_OBJECT(EtherDev)
|
|||
addr);
|
||||
}
|
||||
|
||||
REGISTER_SIM_OBJECT("EtherDev", EtherDev)
|
||||
REGISTER_SIM_OBJECT("NSGigE", NSGigE)
|
||||
|
|
|
|||
|
|
@ -96,7 +96,7 @@ struct dp_rom {
|
|||
};
|
||||
|
||||
class IntrControl;
|
||||
class EtherDevInt;
|
||||
class NSGigEInt;
|
||||
class PhysicalMemory;
|
||||
class BaseInterface;
|
||||
class HierParams;
|
||||
|
|
@ -106,7 +106,7 @@ class PciConfigAll;
|
|||
/**
|
||||
* NS DP82830 Ethernet device model
|
||||
*/
|
||||
class EtherDev : public PciDev
|
||||
class NSGigE : public PciDev
|
||||
{
|
||||
public:
|
||||
/** Transmit State Machine states */
|
||||
|
|
@ -236,20 +236,20 @@ class EtherDev : public PciDev
|
|||
void txDmaWriteCopy();
|
||||
|
||||
void rxDmaReadDone();
|
||||
friend class EventWrapper<EtherDev, &EtherDev::rxDmaReadDone>;
|
||||
EventWrapper<EtherDev, &EtherDev::rxDmaReadDone> rxDmaReadEvent;
|
||||
friend class EventWrapper<NSGigE, &NSGigE::rxDmaReadDone>;
|
||||
EventWrapper<NSGigE, &NSGigE::rxDmaReadDone> rxDmaReadEvent;
|
||||
|
||||
void rxDmaWriteDone();
|
||||
friend class EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone>;
|
||||
EventWrapper<EtherDev, &EtherDev::rxDmaWriteDone> rxDmaWriteEvent;
|
||||
friend class EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone>;
|
||||
EventWrapper<NSGigE, &NSGigE::rxDmaWriteDone> rxDmaWriteEvent;
|
||||
|
||||
void txDmaReadDone();
|
||||
friend class EventWrapper<EtherDev, &EtherDev::txDmaReadDone>;
|
||||
EventWrapper<EtherDev, &EtherDev::txDmaReadDone> txDmaReadEvent;
|
||||
friend class EventWrapper<NSGigE, &NSGigE::txDmaReadDone>;
|
||||
EventWrapper<NSGigE, &NSGigE::txDmaReadDone> txDmaReadEvent;
|
||||
|
||||
void txDmaWriteDone();
|
||||
friend class EventWrapper<EtherDev, &EtherDev::txDmaWriteDone>;
|
||||
EventWrapper<EtherDev, &EtherDev::txDmaWriteDone> txDmaWriteEvent;
|
||||
friend class EventWrapper<NSGigE, &NSGigE::txDmaWriteDone>;
|
||||
EventWrapper<NSGigE, &NSGigE::txDmaWriteDone> txDmaWriteEvent;
|
||||
|
||||
bool dmaDescFree;
|
||||
bool dmaDataFree;
|
||||
|
|
@ -276,19 +276,19 @@ class EtherDev : public PciDev
|
|||
|
||||
void rxKick();
|
||||
Tick rxKickTick;
|
||||
typedef EventWrapper<EtherDev, &EtherDev::rxKick> RxKickEvent;
|
||||
typedef EventWrapper<NSGigE, &NSGigE::rxKick> RxKickEvent;
|
||||
friend class RxKickEvent;
|
||||
|
||||
void txKick();
|
||||
Tick txKickTick;
|
||||
typedef EventWrapper<EtherDev, &EtherDev::txKick> TxKickEvent;
|
||||
typedef EventWrapper<NSGigE, &NSGigE::txKick> TxKickEvent;
|
||||
friend class TxKickEvent;
|
||||
|
||||
/**
|
||||
* Retransmit event
|
||||
*/
|
||||
void transmit();
|
||||
typedef EventWrapper<EtherDev, &EtherDev::transmit> TxEvent;
|
||||
typedef EventWrapper<NSGigE, &NSGigE::transmit> TxEvent;
|
||||
friend class TxEvent;
|
||||
TxEvent txEvent;
|
||||
|
||||
|
|
@ -323,7 +323,7 @@ class EtherDev : public PciDev
|
|||
void cpuInterrupt();
|
||||
void cpuIntrClear();
|
||||
|
||||
typedef EventWrapper<EtherDev, &EtherDev::cpuInterrupt> IntrEvent;
|
||||
typedef EventWrapper<NSGigE, &NSGigE::cpuInterrupt> IntrEvent;
|
||||
friend class IntrEvent;
|
||||
IntrEvent *intrEvent;
|
||||
|
||||
|
|
@ -335,10 +335,10 @@ class EtherDev : public PciDev
|
|||
bool ipChecksum(PacketPtr packet, bool gen);
|
||||
uint16_t checksumCalc(uint16_t *pseudo, uint16_t *buf, uint32_t len);
|
||||
|
||||
EtherDevInt *interface;
|
||||
NSGigEInt *interface;
|
||||
|
||||
public:
|
||||
EtherDev(const std::string &name, IntrControl *i, Tick intr_delay,
|
||||
NSGigE(const std::string &name, IntrControl *i, Tick intr_delay,
|
||||
PhysicalMemory *pmem, Tick tx_delay, Tick rx_delay,
|
||||
MemoryController *mmu, HierParams *hier, Bus *header_bus,
|
||||
Bus *payload_bus, Tick pio_latency, bool dma_desc_free,
|
||||
|
|
@ -346,7 +346,7 @@ class EtherDev : public PciDev
|
|||
Tick dma_read_factor, Tick dma_write_factor, PciConfigAll *cf,
|
||||
PciConfigData *cd, Tsunami *t, uint32_t bus, uint32_t dev,
|
||||
uint32_t func, bool rx_filter, const int eaddr[6], Addr addr);
|
||||
~EtherDev();
|
||||
~NSGigE();
|
||||
|
||||
virtual void WriteConfig(int offset, int size, uint32_t data);
|
||||
virtual void ReadConfig(int offset, int size, uint8_t *data);
|
||||
|
|
@ -360,7 +360,7 @@ class EtherDev : public PciDev
|
|||
bool recvPacket(PacketPtr packet);
|
||||
void transferDone();
|
||||
|
||||
void setInterface(EtherDevInt *i) { assert(!interface); interface = i; }
|
||||
void setInterface(NSGigEInt *i) { assert(!interface); interface = i; }
|
||||
|
||||
virtual void serialize(std::ostream &os);
|
||||
virtual void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
|
@ -388,13 +388,13 @@ class EtherDev : public PciDev
|
|||
/*
|
||||
* Ethernet Interface for an Ethernet Device
|
||||
*/
|
||||
class EtherDevInt : public EtherInt
|
||||
class NSGigEInt : public EtherInt
|
||||
{
|
||||
private:
|
||||
EtherDev *dev;
|
||||
NSGigE *dev;
|
||||
|
||||
public:
|
||||
EtherDevInt(const std::string &name, EtherDev *d)
|
||||
NSGigEInt(const std::string &name, NSGigE *d)
|
||||
: EtherInt(name), dev(d) { dev->setInterface(this); }
|
||||
|
||||
virtual bool recvPacket(PacketPtr &pkt) { return dev->recvPacket(pkt); }
|
||||
|
|
|
|||
|
|
@ -39,7 +39,7 @@
|
|||
|
||||
class IdeController;
|
||||
class TlaserClock;
|
||||
class EtherDev;
|
||||
class NSGigE;
|
||||
class TsunamiCChip;
|
||||
class TsunamiPChip;
|
||||
class TsunamiIO;
|
||||
|
|
@ -67,7 +67,7 @@ class Tsunami : public Platform
|
|||
/** Pointer to the disk controller device */
|
||||
IdeController *disk_controller;
|
||||
/** Pointer to the ethernet controller device */
|
||||
EtherDev *ethernet;
|
||||
NSGigE *ethernet;
|
||||
|
||||
/** Pointer to the Tsunami CChip.
|
||||
* The chip contains some configuration information and
|
||||
|
|
|
|||
|
|
@ -311,6 +311,8 @@ struct SystemCalls<Linux>
|
|||
StandardNumber
|
||||
};
|
||||
|
||||
static const int Number = StandardNumber;
|
||||
|
||||
static const char *name(int num);
|
||||
|
||||
static bool validSyscallNumber(int num) {
|
||||
|
|
|
|||
Loading…
Reference in a new issue