add to instruction test sttw instruction
--HG-- extra : convert_revision : 16efbe12e609a909a589505ad6c473eb44c38f9c
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4 changed files with 16 additions and 21 deletions
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@ -1,11 +1,7 @@
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[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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dummy=0
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[system]
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type=System
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@ -1,9 +1,6 @@
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[root]
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type=Root
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clock=1000000000000
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max_tick=0
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progress_interval=0
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output_file=cout
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dummy=0
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[system.physmem]
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type=PhysicalMemory
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@ -1,18 +1,18 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 104057 # Simulator instruction rate (inst/s)
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host_mem_usage 179368 # Number of bytes of host memory used
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host_seconds 0.10 # Real time elapsed on the host
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host_tick_rate 103746 # Simulator tick rate (ticks/s)
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host_inst_rate 65718 # Simulator instruction rate (inst/s)
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host_mem_usage 179556 # Number of bytes of host memory used
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host_seconds 0.17 # Real time elapsed on the host
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host_tick_rate 65601 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 10367 # Number of instructions simulated
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sim_insts 11001 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 10366 # Number of ticks simulated
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sim_ticks 11000 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 10367 # number of cpu cycles simulated
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system.cpu.num_insts 10367 # Number of instructions executed
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system.cpu.num_refs 2607 # Number of memory references
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system.cpu.numCycles 11001 # number of cpu cycles simulated
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system.cpu.num_insts 11001 # Number of instructions executed
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system.cpu.num_refs 2760 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
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---------- End Simulation Statistics ----------
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@ -7,6 +7,7 @@ CASX FAIL: Passed
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CASX WORK: Passed
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LDTX: Passed
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LDTW: Passed
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STTW: Passed
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Done
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M5 Simulator System
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@ -15,8 +16,9 @@ The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Mar 6 2007 15:43:35
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M5 started Tue Mar 6 15:52:39 2007
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M5 compiled Mar 29 2007 15:29:35
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M5 started Thu Mar 29 15:39:35 2007
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M5 executing on zeep
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command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
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Exiting @ tick 10366 because target called exit()
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Global frequency set at 1000000000000 ticks per second
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Exiting @ tick 11000 because target called exit()
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