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ARM: When changing the CPSR and branching, make sure the branch is second.

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Gabe Black 2010-06-02 12:58:09 -05:00
parent 68f2908a70
commit 36eeee0133
1 changed files with 39 additions and 39 deletions
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78
src/arch/arm/isa/operands.isa
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@ -88,72 +88,72 @@ let {{
def operands {{ def operands {{
#Abstracted integer reg operands #Abstracted integer reg operands
'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0, 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite), maybePCRead, maybeIWPCWrite),
'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
maybePCRead, maybeAIWPCWrite), maybePCRead, maybeAIWPCWrite),
'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0), 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
maybeAlignedPCRead, maybePCWrite), maybeAlignedPCRead, maybePCWrite),
'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0), 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
maybePCRead, maybePCWrite), maybePCRead, maybePCWrite),
#General Purpose Integer Reg Operands #General Purpose Integer Reg Operands
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
#Register fields for microops #Register fields for microops
'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
maybePCRead, maybeIWPCWrite), maybePCRead, maybeIWPCWrite),
'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
#General Purpose Floating Point Reg Operands #General Purpose Floating Point Reg Operands
'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
#Memory Operand #Memory Operand
'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeNPC), readNPC, writeNPC),
'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, forceNPC), readNPC, forceNPC),
'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
readNPC, writeIWNPC), readNPC, writeIWNPC),
}}; }};