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SE/FS: Use the new FullSystem constant where possible.

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This commit is contained in:
Gabe Black 2011-09-30 00:27:16 -07:00
parent 4fcf8e9959
commit 35e20c7470
17 changed files with 40 additions and 32 deletions
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10
src/arch/alpha/isa/decoder.isa
View file

@ -202,8 +202,8 @@ decode OPCODE default Unknown::unknown() {
0x6c: decode RA { 0x6c: decode RA {
31: decode IMM { 31: decode IMM {
1: decode INTIMM { 1: decode INTIMM {
// return EV5 for FULL_SYSTEM and EV6 otherwise // return EV5 for FullSystem and EV6 otherwise
1: implver({{ Rc = FULL_SYSTEM ? 1 : 2 }}); 1: implver({{ Rc = FullSystem ? 1 : 2 }});
} }
} }
} }
@ -780,7 +780,7 @@ decode OPCODE default Unknown::unknown() {
* the parser to understand that. * the parser to understand that.
*/ */
uint64_t unused_var M5_VAR_USED = Rb; uint64_t unused_var M5_VAR_USED = Rb;
Ra = FULL_SYSTEM ? xc->readMiscReg(IPR_CC) : curTick(); Ra = FullSystem ? xc->readMiscReg(IPR_CC) : curTick();
}}, IsUnverifiable); }}, IsUnverifiable);
// All of the barrier instructions below do nothing in // All of the barrier instructions below do nothing in
@ -805,14 +805,14 @@ decode OPCODE default Unknown::unknown() {
0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp);
} }
0xe000: decode FULL_SYSTEM { 0xe000: decode FullSystem {
0: FailUnimpl::rc_se(); 0: FailUnimpl::rc_se();
default: BasicOperate::rc({{ default: BasicOperate::rc({{
Ra = IntrFlag; Ra = IntrFlag;
IntrFlag = 0; IntrFlag = 0;
}}, IsNonSpeculative, IsUnverifiable); }}, IsNonSpeculative, IsUnverifiable);
} }
0xf000: decode FULL_SYSTEM { 0xf000: decode FullSystem {
0: FailUnimpl::rs_se(); 0: FailUnimpl::rs_se();
default: BasicOperate::rs({{ default: BasicOperate::rs({{
Ra = IntrFlag; Ra = IntrFlag;

2
src/arch/alpha/isa/fp.isa
View file

@ -45,7 +45,7 @@ output exec {{
inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc) inline Fault checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
Fault fault = NoFault; // dummy... this ipr access should not fault Fault fault = NoFault; // dummy... this ipr access should not fault
if (FULL_SYSTEM && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) { if (FullSystem && !ICSR_FPE(xc->readMiscReg(IPR_ICSR))) {
fault = new FloatEnableFault; fault = new FloatEnableFault;
} }
return fault; return fault;

2
src/arch/alpha/isa/main.isa
View file

@ -64,6 +64,7 @@ output decoder {{
#include "config/ss_compatible_fp.hh" #include "config/ss_compatible_fp.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget() #include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh" #include "mem/packet.hh"
#include "sim/full_system.hh"
using namespace AlphaISA; using namespace AlphaISA;
}}; }};
@ -81,6 +82,7 @@ output exec {{
#include "cpu/exetrace.hh" #include "cpu/exetrace.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh" #include "mem/packet_access.hh"
#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh" #include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"

3
src/arch/alpha/tlb.cc
View file

@ -42,6 +42,7 @@
#include "base/trace.hh" #include "base/trace.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "debug/TLB.hh" #include "debug/TLB.hh"
#include "sim/full_system.hh"
using namespace std; using namespace std;
@ -370,7 +371,7 @@ Fault
TLB::translateInst(RequestPtr req, ThreadContext *tc) TLB::translateInst(RequestPtr req, ThreadContext *tc)
{ {
//If this is a pal pc, then set PHYSICAL //If this is a pal pc, then set PHYSICAL
if (FULL_SYSTEM && PcPAL(req->getPC())) if (FullSystem && PcPAL(req->getPC()))
req->setFlags(Request::PHYSICAL); req->setFlags(Request::PHYSICAL);
if (PcPAL(req->getPC())) { if (PcPAL(req->getPC())) {

4
src/arch/mips/faults.cc
View file

@ -134,7 +134,7 @@ MipsFaultBase::setExceptionState(ThreadContext *tc, uint8_t excCode)
void void
MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst) MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
if (FULL_SYSTEM) { if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
setExceptionState(tc, code()); setExceptionState(tc, code());
tc->pcState(vect(tc)); tc->pcState(vect(tc));
@ -146,7 +146,7 @@ MipsFaultBase::invoke(ThreadContext *tc, StaticInstPtr inst)
void void
ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst) ResetFault::invoke(ThreadContext *tc, StaticInstPtr inst)
{ {
if (FULL_SYSTEM) { if (FullSystem) {
DPRINTF(MipsPRA, "%s encountered.\n", name()); DPRINTF(MipsPRA, "%s encountered.\n", name());
/* All reset activity must be invoked from here */ /* All reset activity must be invoked from here */
Addr handler = vect(tc); Addr handler = vect(tc);

7
src/arch/mips/faults.hh
View file

@ -38,6 +38,7 @@
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "debug/MipsPRA.hh" #include "debug/MipsPRA.hh"
#include "sim/faults.hh" #include "sim/faults.hh"
#include "sim/full_system.hh"
namespace MipsISA namespace MipsISA
{ {
@ -163,7 +164,7 @@ class CoprocessorUnusableFault : public MipsFault<CoprocessorUnusableFault>
StaticInstPtr inst = StaticInst::nullStaticInstPtr) StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{ {
MipsFault<CoprocessorUnusableFault>::invoke(tc, inst); MipsFault<CoprocessorUnusableFault>::invoke(tc, inst);
if (FULL_SYSTEM) { if (FullSystem) {
CauseReg cause = tc->readMiscReg(MISCREG_CAUSE); CauseReg cause = tc->readMiscReg(MISCREG_CAUSE);
cause.ce = coProcID; cause.ce = coProcID;
tc->setMiscReg(MISCREG_CAUSE, cause); tc->setMiscReg(MISCREG_CAUSE, cause);
@ -197,7 +198,7 @@ class AddressFault : public MipsFault<T>
StaticInstPtr inst = StaticInst::nullStaticInstPtr) StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{ {
MipsFault<T>::invoke(tc, inst); MipsFault<T>::invoke(tc, inst);
if (FULL_SYSTEM) if (FullSystem)
tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr); tc->setMiscRegNoEffect(MISCREG_BADVADDR, vaddr);
} }
}; };
@ -249,7 +250,7 @@ class TlbFault : public AddressFault<T>
invoke(ThreadContext * tc, invoke(ThreadContext * tc,
StaticInstPtr inst = StaticInst::nullStaticInstPtr) StaticInstPtr inst = StaticInst::nullStaticInstPtr)
{ {
if (FULL_SYSTEM) { if (FullSystem) {
DPRINTF(MipsPRA, "Fault %s encountered.\n", name()); DPRINTF(MipsPRA, "Fault %s encountered.\n", name());
tc->pcState(this->vect(tc)); tc->pcState(this->vect(tc));
setTlbExceptionState(tc, this->code()); setTlbExceptionState(tc, this->code());

10
src/arch/mips/isa/decoder.isa
View file

@ -163,7 +163,7 @@ decode OPCODE_HI default Unknown::unknown() {
format BasicOp { format BasicOp {
0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }});
0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }});
0x4: decode FULL_SYSTEM { 0x4: decode FullSystem {
0: syscall_se({{ xc->syscall(R2); }}, 0: syscall_se({{ xc->syscall(R2); }},
IsSerializeAfter, IsNonSpeculative); IsSerializeAfter, IsNonSpeculative);
default: syscall({{ fault = new SystemCallFault(); }}); default: syscall({{ fault = new SystemCallFault(); }});
@ -212,7 +212,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: add({{ 0x0: add({{
IntReg result; IntReg result;
Rd = result = Rs + Rt; Rd = result = Rs + Rt;
if (FULL_SYSTEM && if (FullSystem &&
findOverflow(32, result, Rs, Rt)) { findOverflow(32, result, Rs, Rt)) {
fault = new IntegerOverflowFault(); fault = new IntegerOverflowFault();
} }
@ -221,7 +221,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x2: sub({{ 0x2: sub({{
IntReg result; IntReg result;
Rd = result = Rs - Rt; Rd = result = Rs - Rt;
if (FULL_SYSTEM && if (FullSystem &&
findOverflow(32, result, Rs, ~Rt)) { findOverflow(32, result, Rs, ~Rt)) {
fault = new IntegerOverflowFault(); fault = new IntegerOverflowFault();
} }
@ -325,7 +325,7 @@ decode OPCODE_HI default Unknown::unknown() {
0x0: addi({{ 0x0: addi({{
IntReg result; IntReg result;
Rt = result = Rs + imm; Rt = result = Rs + imm;
if (FULL_SYSTEM && if (FullSystem &&
findOverflow(32, result, Rs, imm)) { findOverflow(32, result, Rs, imm)) {
fault = new IntegerOverflowFault(); fault = new IntegerOverflowFault();
} }
@ -2433,7 +2433,7 @@ decode OPCODE_HI default Unknown::unknown() {
} }
} }
0x3: decode OP default FailUnimpl::rdhwr() { 0x3: decode OP default FailUnimpl::rdhwr() {
0x0: decode FULL_SYSTEM { 0x0: decode FullSystem {
0: decode RD { 0: decode RD {
29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); 29: BasicOp::rdhwr_se({{ Rt = TpValue; }});
} }

8
src/arch/mips/isa/formats/control.isa
View file

@ -128,7 +128,7 @@ def template ControlTLBExecute {{
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
if (FULL_SYSTEM) { if (FullSystem) {
if (isCoprocessor0Enabled(xc)) { if (isCoprocessor0Enabled(xc)) {
if(isMMUTLB(xc)){ if(isMMUTLB(xc)){
%(code)s; %(code)s;
@ -176,7 +176,7 @@ output exec {{
bool bool
isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num) isCoprocessorEnabled(%(CPU_exec_context)s *xc, unsigned cop_num)
{ {
if (!FULL_SYSTEM) if (!FullSystem)
return true; return true;
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
@ -198,7 +198,7 @@ output exec {{
bool inline bool inline
isCoprocessor0Enabled(%(CPU_exec_context)s *xc) isCoprocessor0Enabled(%(CPU_exec_context)s *xc)
{ {
if (FULL_SYSTEM) { if (FullSystem) {
MiscReg Stat = xc->readMiscReg(MISCREG_STATUS); MiscReg Stat = xc->readMiscReg(MISCREG_STATUS);
MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG); MiscReg Dbg = xc->readMiscReg(MISCREG_DEBUG);
// In Stat, EXL, ERL or CU0 set, CP0 accessible // In Stat, EXL, ERL or CU0 set, CP0 accessible
@ -215,7 +215,7 @@ output exec {{
isMMUTLB(%(CPU_exec_context)s *xc) isMMUTLB(%(CPU_exec_context)s *xc)
{ {
MiscReg Config = xc->readMiscReg(MISCREG_CONFIG); MiscReg Config = xc->readMiscReg(MISCREG_CONFIG);
return FULL_SYSTEM && (Config & 0x380) == 0x80; return FullSystem && (Config & 0x380) == 0x80;
} }
}}; }};

4
src/arch/mips/isa/formats/dsp.isa
View file

@ -143,7 +143,7 @@ output exec {{
bool bool
isDspEnabled(%(CPU_exec_context)s *xc) isDspEnabled(%(CPU_exec_context)s *xc)
{ {
return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_STATUS), 24); return !FullSystem || bits(xc->readMiscReg(MISCREG_STATUS), 24);
} }
}}; }};
@ -151,7 +151,7 @@ output exec {{
bool bool
isDspPresent(%(CPU_exec_context)s *xc) isDspPresent(%(CPU_exec_context)s *xc)
{ {
return !FULL_SYSTEM || bits(xc->readMiscReg(MISCREG_CONFIG3), 10); return !FullSystem || bits(xc->readMiscReg(MISCREG_CONFIG3), 10);
} }
}}; }};

4
src/arch/mips/isa/formats/fp.isa
View file

@ -174,7 +174,7 @@ def template FloatingPointExecute {{
//When is the right time to reset cause bits? //When is the right time to reset cause bits?
//start of every instruction or every cycle? //start of every instruction or every cycle?
if (FULL_SYSTEM) if (FullSystem)
fpResetCauseBits(xc); fpResetCauseBits(xc);
%(op_decl)s; %(op_decl)s;
%(op_rd)s; %(op_rd)s;
@ -191,7 +191,7 @@ def template FloatingPointExecute {{
//Check for IEEE 754 FP Exceptions //Check for IEEE 754 FP Exceptions
//fault = fpNanOperands((FPOp*)this, xc, Fd, traceData); //fault = fpNanOperands((FPOp*)this, xc, Fd, traceData);
bool invalid_op = false; bool invalid_op = false;
if (FULL_SYSTEM) { if (FullSystem) {
invalid_op = invalid_op =
fpInvalidOp((FPOp*)this, xc, Fd, traceData); fpInvalidOp((FPOp*)this, xc, Fd, traceData);
} }

6
src/arch/mips/isa/formats/unimp.isa
View file

@ -193,7 +193,7 @@ output exec {{
CP0Unimplemented::execute(%(CPU_exec_context)s *xc, CP0Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
if (FULL_SYSTEM) { if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0)) if (!isCoprocessorEnabled(xc, 0))
return new CoprocessorUnusableFault(0); return new CoprocessorUnusableFault(0);
else else
@ -210,7 +210,7 @@ output exec {{
CP1Unimplemented::execute(%(CPU_exec_context)s *xc, CP1Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
if (FULL_SYSTEM) { if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1)) if (!isCoprocessorEnabled(xc, 1))
return new CoprocessorUnusableFault(1); return new CoprocessorUnusableFault(1);
else else
@ -227,7 +227,7 @@ output exec {{
CP2Unimplemented::execute(%(CPU_exec_context)s *xc, CP2Unimplemented::execute(%(CPU_exec_context)s *xc,
Trace::InstRecord *traceData) const Trace::InstRecord *traceData) const
{ {
if (FULL_SYSTEM) { if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2)) if (!isCoprocessorEnabled(xc, 2))
return new CoprocessorUnusableFault(2); return new CoprocessorUnusableFault(2);
else else

2
src/arch/mips/isa/includes.isa
View file

@ -58,6 +58,7 @@ output decoder {{
#include "base/cprintf.hh" #include "base/cprintf.hh"
#include "cpu/thread_context.hh" #include "cpu/thread_context.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "sim/full_system.hh"
#if defined(linux) #if defined(linux)
#include <fenv.h> #include <fenv.h>
#endif #endif
@ -90,6 +91,7 @@ output exec {{
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh" #include "mem/packet_access.hh"
#include "sim/eventq.hh" #include "sim/eventq.hh"
#include "sim/full_system.hh"
#include "sim/sim_events.hh" #include "sim/sim_events.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"

2
src/arch/sparc/isa/base.isa
View file

@ -566,7 +566,7 @@ output exec {{
static inline Fault static inline Fault
checkFpEnableFault(%(CPU_exec_context)s *xc) checkFpEnableFault(%(CPU_exec_context)s *xc)
{ {
if (FULL_SYSTEM) { if (FullSystem) {
if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef && if (xc->readMiscReg(MISCREG_PSTATE) & PSTATE::pef &&
xc->readMiscReg(MISCREG_FPRS) & 0x4) { xc->readMiscReg(MISCREG_FPRS) & 0x4) {
return NoFault; return NoFault;

1
src/arch/sparc/isa/includes.isa
View file

@ -74,6 +74,7 @@ output exec {{
#include "debug/Sparc.hh" #include "debug/Sparc.hh"
#include "mem/packet.hh" #include "mem/packet.hh"
#include "mem/packet_access.hh" #include "mem/packet_access.hh"
#include "sim/full_system.hh"
#include "sim/pseudo_inst.hh" #include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh" #include "sim/sim_exit.hh"

2
src/arch/x86/isa/decoder/one_byte_opcodes.isa
View file

@ -394,7 +394,7 @@
default: Inst::RET_FAR(); default: Inst::RET_FAR();
} }
0x4: int3(); 0x4: int3();
0x5: decode FULL_SYSTEM default int_Ib() { 0x5: decode FullSystem default int_Ib() {
0: decode IMMEDIATE { 0: decode IMMEDIATE {
// Really only the LSB matters, but the predecoder // Really only the LSB matters, but the predecoder
// will sign extend it, and there's no easy way to // will sign extend it, and there's no easy way to

4
src/arch/x86/isa/decoder/two_byte_opcodes.isa
View file

@ -216,7 +216,7 @@
default: Inst::UD2(); default: Inst::UD2();
} }
} }
0x05: decode FULL_SYSTEM { 0x05: decode FullSystem {
0: SyscallInst::syscall('xc->syscall(Rax)', 0: SyscallInst::syscall('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter); IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: decode MODE_MODE { default: decode MODE_MODE {
@ -398,7 +398,7 @@
0x1: Inst::RDTSC(); 0x1: Inst::RDTSC();
0x2: Inst::RDMSR(); 0x2: Inst::RDMSR();
0x3: rdpmc(); 0x3: rdpmc();
0x4: decode FULL_SYSTEM { 0x4: decode FullSystem {
0: SyscallInst::sysenter('xc->syscall(Rax)', 0: SyscallInst::sysenter('xc->syscall(Rax)',
IsSyscall, IsNonSpeculative, IsSerializeAfter); IsSyscall, IsNonSpeculative, IsSerializeAfter);
default: sysenter(); default: sysenter();

1
src/arch/x86/isa/includes.isa
View file

@ -84,6 +84,7 @@ output decoder {{
#include "base/misc.hh" #include "base/misc.hh"
#include "cpu/thread_context.hh" // for Jump::branchTarget() #include "cpu/thread_context.hh" // for Jump::branchTarget()
#include "mem/packet.hh" #include "mem/packet.hh"
#include "sim/full_system.hh"
#if defined(linux) || defined(__APPLE__) #if defined(linux) || defined(__APPLE__)
#include <fenv.h> #include <fenv.h>