Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.
src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
Push more default options to the Python object level as they are rarely changed.
--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb
This commit is contained in:
Kevin Lim
parent
807afe8292
commit
35ab2296d3
4 changed files with 144 additions and 9 deletions
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@ -10,6 +10,6 @@ class RawDiskImage(DiskImage):
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class CowDiskImage(DiskImage):
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type = 'CowDiskImage'
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child = Param.DiskImage("child image")
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child = Param.DiskImage(RawDiskImage(read_only=True),
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"child image")
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table_size = Param.Int(65536, "initial table size")
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image_file = ''
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@ -1,7 +1,7 @@
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from m5 import build_env
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from m5.config import *
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from Device import DmaDevice
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from Pci import PciDevice
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from Pci import PciDevice, PciConfigData
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class EtherInt(SimObject):
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type = 'EtherInt'
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@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
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tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
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rss = Param.Bool(False, "Receive Side Scaling")
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class NSGigEPciData(PciConfigData):
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VendorID = 0x100B
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DeviceID = 0x0022
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000001
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '256B'
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BAR1Size = '4kB'
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class NSGigE(EtherDevBase):
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type = 'NSGigE'
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@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
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dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
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dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
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configdata = NSGigEPciData()
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class NSGigEInt(EtherInt):
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type = 'NSGigEInt'
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device = Param.NSGigE("Ethernet device of this interface")
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class SinicPciData(PciConfigData):
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VendorID = 0x1291
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DeviceID = 0x1293
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Status = 0x0290
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SubClassCode = 0x00
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ClassCode = 0x02
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ProgIF = 0x00
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BAR0 = 0x00000000
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BAR1 = 0x00000000
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BAR2 = 0x00000000
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BAR3 = 0x00000000
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BAR4 = 0x00000000
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BAR5 = 0x00000000
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MaximumLatency = 0x34
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MinimumGrant = 0xb0
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InterruptLine = 0x1e
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InterruptPin = 0x01
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BAR0Size = '64kB'
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class Sinic(EtherDevBase):
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type = 'Sinic'
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@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
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delay_copy = Param.Bool(False, "Delayed copy transmit")
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virtual_addr = Param.Bool(False, "Virtual addressing")
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configdata = SinicPciData()
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class SinicInt(EtherInt):
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type = 'SinicInt'
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device = Param.Sinic("Ethernet device of this interface")
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@ -1,8 +1,31 @@
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from m5.config import *
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from Pci import PciDevice
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from Pci import PciDevice, PciConfigData
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class IdeID(Enum): vals = ['master', 'slave']
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class IdeControllerPciData(PciConfigData):
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VendorID = 0x8086
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DeviceID = 0x7111
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Command = 0x0
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Status = 0x280
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Revision = 0x0
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ClassCode = 0x01
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SubClassCode = 0x01
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ProgIF = 0x85
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BAR0 = 0x00000001
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BAR1 = 0x00000001
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BAR2 = 0x00000001
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BAR3 = 0x00000001
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BAR4 = 0x00000001
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BAR5 = 0x00000001
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InterruptLine = 0x1f
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InterruptPin = 0x01
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BAR0Size = '8B'
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BAR1Size = '4B'
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BAR2Size = '8B'
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BAR3Size = '4B'
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BAR4Size = '16B'
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class IdeDisk(SimObject):
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type = 'IdeDisk'
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delay = Param.Latency('1us', "Fixed disk delay in microseconds")
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@ -12,3 +35,5 @@ class IdeDisk(SimObject):
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class IdeController(PciDevice):
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type = 'IdeController'
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disks = VectorParam.IdeDisk("IDE disks attached to this controller")
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configdata =IdeControllerPciData()
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@ -1,11 +1,10 @@
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from m5.config import *
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from Device import BasicPioDevice
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from Platform import Platform
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class Tsunami(Platform):
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type = 'Tsunami'
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# pciconfig = Param.PciConfigAll("PCI configuration")
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system = Param.System(Parent.any, "system")
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from AlphaConsole import AlphaConsole
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from Uart import Uart8250
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from Pci import PciConfigAll
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from BadDevice import BadDevice
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class TsunamiCChip(BasicPioDevice):
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type = 'TsunamiCChip'
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@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice):
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class TsunamiPChip(BasicPioDevice):
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type = 'TsunamiPChip'
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tsunami = Param.Tsunami(Parent.any, "Tsunami")
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class Tsunami(Platform):
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type = 'Tsunami'
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system = Param.System(Parent.any, "system")
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cchip = TsunamiCChip(pio_addr=0x801a0000000)
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pchip = TsunamiPChip(pio_addr=0x80180000000)
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pciconfig = PciConfigAll()
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fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
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fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
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fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
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fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
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fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
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fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
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fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
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fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
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fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
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fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
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fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
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fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
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fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
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fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
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fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
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fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
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fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
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fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
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fake_ata1 = IsaFake(pio_addr=0x801fc000170)
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fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
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io = TsunamiIO(pio_addr=0x801fc000000)
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uart = Uart8250(pio_addr=0x801fc0003f8)
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console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
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# Attach I/O devices to specified bus object. Can't do this
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# earlier, since the bus object itself is typically defined at the
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# System level.
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def attachIO(self, bus):
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self.cchip.pio = bus.port
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self.pchip.pio = bus.port
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self.pciconfig.pio = bus.default
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self.fake_sm_chip.pio = bus.port
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self.fake_uart1.pio = bus.port
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self.fake_uart2.pio = bus.port
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self.fake_uart3.pio = bus.port
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self.fake_uart4.pio = bus.port
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self.fake_ppc.pio = bus.port
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self.fake_OROM.pio = bus.port
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self.fake_pnp_addr.pio = bus.port
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self.fake_pnp_write.pio = bus.port
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self.fake_pnp_read0.pio = bus.port
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self.fake_pnp_read1.pio = bus.port
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self.fake_pnp_read2.pio = bus.port
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self.fake_pnp_read3.pio = bus.port
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self.fake_pnp_read4.pio = bus.port
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self.fake_pnp_read5.pio = bus.port
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self.fake_pnp_read6.pio = bus.port
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self.fake_pnp_read7.pio = bus.port
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self.fake_ata0.pio = bus.port
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self.fake_ata1.pio = bus.port
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self.fb.pio = bus.port
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self.io.pio = bus.port
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self.uart.pio = bus.port
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self.console.pio = bus.port
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