Push more default options to the Python object level as they are rarely changed. These are the changes that Steve was working on.

src/python/m5/objects/DiskImage.py:
src/python/m5/objects/Ethernet.py:
src/python/m5/objects/Ide.py:
src/python/m5/objects/Tsunami.py:
    Push more default options to the Python object level as they are rarely changed.

--HG--
extra : convert_revision : 963eb7a34cd04529b3c5f24b92904ab725c93efb

src/python/m5/objects/DiskImage.py

@@ -10,6 +10,6 @@ class RawDiskImage(DiskImage):
 
 class CowDiskImage(DiskImage):
     type = 'CowDiskImage'
-    child = Param.DiskImage("child image")
+    child = Param.DiskImage(RawDiskImage(read_only=True),
+                            "child image")
     table_size = Param.Int(65536, "initial table size")
-    image_file = ''

src/python/m5/objects/Ethernet.py

@@ -1,7 +1,7 @@
 from m5 import build_env
 from m5.config import *
 from Device import DmaDevice
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
 
 class EtherInt(SimObject):
     type = 'EtherInt'
@@ -84,6 +84,26 @@ class EtherDevBase(PciDevice):
     tx_thread = Param.Bool(False, "dedicated kernel threads for receive")
     rss = Param.Bool(False, "Receive Side Scaling")
 
+class NSGigEPciData(PciConfigData):
+    VendorID = 0x100B
+    DeviceID = 0x0022
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000001
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '256B'
+    BAR1Size = '4kB'
+
 class NSGigE(EtherDevBase):
     type = 'NSGigE'
 
@@ -91,11 +111,32 @@ class NSGigE(EtherDevBase):
     dma_desc_free = Param.Bool(False, "DMA of Descriptors is free")
     dma_no_allocate = Param.Bool(True, "Should we allocate cache on read")
 
+    configdata = NSGigEPciData()
+
 
 class NSGigEInt(EtherInt):
     type = 'NSGigEInt'
     device = Param.NSGigE("Ethernet device of this interface")
 
+class SinicPciData(PciConfigData):
+    VendorID = 0x1291
+    DeviceID = 0x1293
+    Status = 0x0290
+    SubClassCode = 0x00
+    ClassCode = 0x02
+    ProgIF = 0x00
+    BAR0 = 0x00000000
+    BAR1 = 0x00000000
+    BAR2 = 0x00000000
+    BAR3 = 0x00000000
+    BAR4 = 0x00000000
+    BAR5 = 0x00000000
+    MaximumLatency = 0x34
+    MinimumGrant = 0xb0
+    InterruptLine = 0x1e
+    InterruptPin = 0x01
+    BAR0Size = '64kB'
+
 class Sinic(EtherDevBase):
     type = 'Sinic'
 
@@ -111,6 +152,8 @@ class Sinic(EtherDevBase):
     delay_copy = Param.Bool(False, "Delayed copy transmit")
     virtual_addr = Param.Bool(False, "Virtual addressing")
 
+    configdata = SinicPciData()
+
 class SinicInt(EtherInt):
     type = 'SinicInt'
     device = Param.Sinic("Ethernet device of this interface")

src/python/m5/objects/Ide.py

@@ -1,8 +1,31 @@
 from m5.config import *
-from Pci import PciDevice
+from Pci import PciDevice, PciConfigData
 
 class IdeID(Enum): vals = ['master', 'slave']
 
+class IdeControllerPciData(PciConfigData):
+    VendorID = 0x8086
+    DeviceID = 0x7111
+    Command = 0x0
+    Status = 0x280
+    Revision = 0x0
+    ClassCode = 0x01
+    SubClassCode = 0x01
+    ProgIF = 0x85
+    BAR0 = 0x00000001
+    BAR1 = 0x00000001
+    BAR2 = 0x00000001
+    BAR3 = 0x00000001
+    BAR4 = 0x00000001
+    BAR5 = 0x00000001
+    InterruptLine = 0x1f
+    InterruptPin = 0x01
+    BAR0Size = '8B'
+    BAR1Size = '4B'
+    BAR2Size = '8B'
+    BAR3Size = '4B'
+    BAR4Size = '16B'
+
 class IdeDisk(SimObject):
     type = 'IdeDisk'
     delay = Param.Latency('1us', "Fixed disk delay in microseconds")
@@ -12,3 +35,5 @@ class IdeDisk(SimObject):
 class IdeController(PciDevice):
     type = 'IdeController'
     disks = VectorParam.IdeDisk("IDE disks attached to this controller")
+
+    configdata =IdeControllerPciData()

src/python/m5/objects/Tsunami.py

@@ -1,11 +1,10 @@
 from m5.config import *
 from Device import BasicPioDevice
 from Platform import Platform
-
+from AlphaConsole import AlphaConsole
-class Tsunami(Platform):
+from Uart import Uart8250
-    type = 'Tsunami'
+from Pci import PciConfigAll
-#    pciconfig = Param.PciConfigAll("PCI configuration")
+from BadDevice import BadDevice
-    system = Param.System(Parent.any, "system")
 
 class TsunamiCChip(BasicPioDevice):
     type = 'TsunamiCChip'
@@ -25,3 +24,71 @@ class TsunamiIO(BasicPioDevice):
 class TsunamiPChip(BasicPioDevice):
     type = 'TsunamiPChip'
     tsunami = Param.Tsunami(Parent.any, "Tsunami")
+
+class Tsunami(Platform):
+    type = 'Tsunami'
+    system = Param.System(Parent.any, "system")
+
+    cchip = TsunamiCChip(pio_addr=0x801a0000000)
+    pchip = TsunamiPChip(pio_addr=0x80180000000)
+    pciconfig = PciConfigAll()
+    fake_sm_chip = IsaFake(pio_addr=0x801fc000370)
+
+    fake_uart1 = IsaFake(pio_addr=0x801fc0002f8)
+    fake_uart2 = IsaFake(pio_addr=0x801fc0003e8)
+    fake_uart3 = IsaFake(pio_addr=0x801fc0002e8)
+    fake_uart4 = IsaFake(pio_addr=0x801fc0003f0)
+
+    fake_ppc = IsaFake(pio_addr=0x801fc0003bc)
+
+    fake_OROM = IsaFake(pio_addr=0x800000a0000, pio_size=0x60000)
+
+    fake_pnp_addr = IsaFake(pio_addr=0x801fc000279)
+    fake_pnp_write = IsaFake(pio_addr=0x801fc000a79)
+    fake_pnp_read0 = IsaFake(pio_addr=0x801fc000203)
+    fake_pnp_read1 = IsaFake(pio_addr=0x801fc000243)
+    fake_pnp_read2 = IsaFake(pio_addr=0x801fc000283)
+    fake_pnp_read3 = IsaFake(pio_addr=0x801fc0002c3)
+    fake_pnp_read4 = IsaFake(pio_addr=0x801fc000303)
+    fake_pnp_read5 = IsaFake(pio_addr=0x801fc000343)
+    fake_pnp_read6 = IsaFake(pio_addr=0x801fc000383)
+    fake_pnp_read7 = IsaFake(pio_addr=0x801fc0003c3)
+
+    fake_ata0 = IsaFake(pio_addr=0x801fc0001f0)
+    fake_ata1 = IsaFake(pio_addr=0x801fc000170)
+
+    fb = BadDevice(pio_addr=0x801fc0003d0, devicename='FrameBuffer')
+    io = TsunamiIO(pio_addr=0x801fc000000)
+    uart = Uart8250(pio_addr=0x801fc0003f8)
+    console = AlphaConsole(pio_addr=0x80200000000, disk=Parent.simple_disk)
+
+    # Attach I/O devices to specified bus object.  Can't do this
+    # earlier, since the bus object itself is typically defined at the
+    # System level.
+    def attachIO(self, bus):
+        self.cchip.pio = bus.port
+        self.pchip.pio = bus.port
+        self.pciconfig.pio = bus.default
+        self.fake_sm_chip.pio = bus.port
+        self.fake_uart1.pio = bus.port
+        self.fake_uart2.pio = bus.port
+        self.fake_uart3.pio = bus.port
+        self.fake_uart4.pio = bus.port
+        self.fake_ppc.pio = bus.port
+        self.fake_OROM.pio = bus.port
+        self.fake_pnp_addr.pio = bus.port
+        self.fake_pnp_write.pio = bus.port
+        self.fake_pnp_read0.pio = bus.port
+        self.fake_pnp_read1.pio = bus.port
+        self.fake_pnp_read2.pio = bus.port
+        self.fake_pnp_read3.pio = bus.port
+        self.fake_pnp_read4.pio = bus.port
+        self.fake_pnp_read5.pio = bus.port
+        self.fake_pnp_read6.pio = bus.port
+        self.fake_pnp_read7.pio = bus.port
+        self.fake_ata0.pio = bus.port
+        self.fake_ata1.pio = bus.port
+        self.fb.pio = bus.port
+        self.io.pio = bus.port
+        self.uart.pio = bus.port
+        self.console.pio = bus.port