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alpha: Stop using 'inorder' and rely entirely on 'minor'

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This patch avoids building the 'inorder' CPU model for any permutation
of ALPHA, and also removes the ALPHA regressions using the 'inorder'
CPU. The 'minor' CPU is already providing a broader test coverage.
This commit is contained in:
Andreas Hansson 2014-09-03 07:42:56 -04:00
parent 83a46bfc09
commit 351e146b37
37 changed files with 6 additions and 6387 deletions
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2
build_opts/ALPHA
View file

@ -1,4 +1,4 @@
TARGET_ISA = 'alpha' TARGET_ISA = 'alpha'
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU,MinorCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MI_example' PROTOCOL = 'MI_example'

2
build_opts/ALPHA_MESI_Two_Level
View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MESI_Two_Level' PROTOCOL = 'MESI_Two_Level'

2
build_opts/ALPHA_MOESI_CMP_directory
View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_directory' PROTOCOL = 'MOESI_CMP_directory'

2
build_opts/ALPHA_MOESI_CMP_token
View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_CMP_token' PROTOCOL = 'MOESI_CMP_token'

2
build_opts/ALPHA_MOESI_hammer
View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'MOESI_hammer' PROTOCOL = 'MOESI_hammer'

2
build_opts/ALPHA_Network_test
View file

@ -1,3 +1,3 @@
SS_COMPATIBLE_FP = 1 SS_COMPATIBLE_FP = 1
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,InOrderCPU' CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'Network_test' PROTOCOL = 'Network_test'

1
tests/SConscript
View file

@ -307,7 +307,6 @@ if env['TARGET_ISA'] == 'alpha':
'twosys-tsunami-simple-atomic', 'twosys-tsunami-simple-atomic',
'tsunami-o3', 'tsunami-o3-dual', 'tsunami-o3', 'tsunami-o3-dual',
'tsunami-minor', 'tsunami-minor-dual', 'tsunami-minor', 'tsunami-minor-dual',
'tsunami-inorder',
'tsunami-switcheroo-full'] 'tsunami-switcheroo-full']
if env['TARGET_ISA'] == 'sparc': if env['TARGET_ISA'] == 'sparc':
configs += ['t1000-simple-atomic', configs += ['t1000-simple-atomic',

43
tests/configs/tsunami-inorder.py
View file

@ -1,43 +0,0 @@
# Copyright (c) 2012 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
# Authors: Andreas Sandberg
from m5.objects import *
from alpha_generic import *
root = LinuxAlphaFSSystemUniprocessor(mem_mode='timing',
mem_class=DDR3_1600_x64,
cpu_class=InOrderCPU).create_root()

346
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -1,346 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=eon chair.control.cook chair.camera chair.surfaces chair.cook.ppm ppm pixels_out.cook
cwd=build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/eon
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

51
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,51 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
getting pixel output filename pixels_out.cook
opening control file chair.control.cook
opening camera file chair.camera
opening surfaces file chair.surfaces
reading data
processing 8parts
Grid measure is 6 by 3.0001 by 6
cell dimension is 0.863065
Creating grid for list of length 21
Grid size = 7 by 4 by 7
Total occupancy = 236
reading control stream
reading camera stream
Writing to chair.cook.ppm
calculating 15 by 15 image with 196 samples
col 0. . .
col 1. . .
col 2. . .
col 3. . .
col 4. . .
col 5. . .
col 6. . .
col 7. . .
col 8. . .
col 9. . .
col 10. . .
col 11. . .
col 12. . .
col 13. . .
col 14. . .
Writing to chair.cook.ppm
0 8 14
1 8 14
2 8 14
3 8 14
4 8 14
5 8 14
6 8 14
7 8 14
8 8 14
9 8 14
10 8 14
11 8 14
12 8 14
13 8 14
14 8 14
warn: ignoring syscall sigprocmask(1, ...)

14
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,14 +0,0 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 16:27:55
gem5 started Jan 22 2014 17:48:27
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/30.eon/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Eon, Version 1.1
info: Increasing stack size by one page.
OO-style eon Time= 0.133333
Exiting @ tick 139926186500 because target called exit()

723
tests/long/se/30.eon/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,723 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.139925 # Number of seconds simulated
sim_ticks 139925460500 # Number of ticks simulated
final_tick 139925460500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 120046 # Simulator instruction rate (inst/s)
host_op_rate 120046 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 42134532 # Simulator tick rate (ticks/s)
host_mem_usage 271408 # Number of bytes of host memory used
host_seconds 3320.92 # Real time elapsed on the host
sim_insts 398664595 # Number of instructions simulated
sim_ops 398664595 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 214976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 254016 # Number of bytes read from this memory
system.physmem.bytes_read::total 468992 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 214976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 214976 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 3359 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 3969 # Number of read requests responded to by this memory
system.physmem.num_reads::total 7328 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 1536361 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 1815367 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 3351727 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 1536361 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 1536361 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 1536361 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 1815367 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 3351727 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 7328 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 7328 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 468992 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 468992 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 507 # Per bank write bursts
system.physmem.perBankRdBursts::1 643 # Per bank write bursts
system.physmem.perBankRdBursts::2 444 # Per bank write bursts
system.physmem.perBankRdBursts::3 597 # Per bank write bursts
system.physmem.perBankRdBursts::4 448 # Per bank write bursts
system.physmem.perBankRdBursts::5 451 # Per bank write bursts
system.physmem.perBankRdBursts::6 505 # Per bank write bursts
system.physmem.perBankRdBursts::7 513 # Per bank write bursts
system.physmem.perBankRdBursts::8 423 # Per bank write bursts
system.physmem.perBankRdBursts::9 395 # Per bank write bursts
system.physmem.perBankRdBursts::10 336 # Per bank write bursts
system.physmem.perBankRdBursts::11 304 # Per bank write bursts
system.physmem.perBankRdBursts::12 416 # Per bank write bursts
system.physmem.perBankRdBursts::13 534 # Per bank write bursts
system.physmem.perBankRdBursts::14 441 # Per bank write bursts
system.physmem.perBankRdBursts::15 371 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 139925387000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 7328 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 4503 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1916 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 608 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 242 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 58 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1345 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 345.790335 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 209.990258 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 340.082178 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 408 30.33% 30.33% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 331 24.61% 54.94% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 167 12.42% 67.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 84 6.25% 73.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 65 4.83% 78.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 45 3.35% 81.78% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 30 2.23% 84.01% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 29 2.16% 86.17% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 186 13.83% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1345 # Bytes accessed per row activation
system.physmem.totQLat 64590750 # Total ticks spent queuing
system.physmem.totMemAccLat 201990750 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 36640000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8814.24 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 27564.24 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 3.35 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 3.35 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.03 # Data bus utilization in percentage
system.physmem.busUtilRead 0.03 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.01 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 5972 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 81.50 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 19094621.59 # Average gap between requests
system.physmem.pageHitRate 81.50 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 133853003250 # Time in different power states
system.physmem.memoryStateTime::REF 4672200000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 1393983000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 3351727 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 4183 # Transaction distribution
system.membus.trans_dist::ReadResp 4183 # Transaction distribution
system.membus.trans_dist::ReadExReq 3145 # Transaction distribution
system.membus.trans_dist::ReadExResp 3145 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 14656 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 14656 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 468992 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 468992 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 468992 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 8819000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 68224500 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 53489674 # Number of BP lookups
system.cpu.branchPred.condPredicted 30685396 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 15149659 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 32882351 # Number of BTB lookups
system.cpu.branchPred.BTBHits 15212538 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 46.263535 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 8007516 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 20 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 94754638 # DTB read hits
system.cpu.dtb.read_misses 21 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 94754659 # DTB read accesses
system.cpu.dtb.write_hits 73521127 # DTB write hits
system.cpu.dtb.write_misses 35 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 73521162 # DTB write accesses
system.cpu.dtb.data_hits 168275765 # DTB hits
system.cpu.dtb.data_misses 56 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 168275821 # DTB accesses
system.cpu.itb.fetch_hits 48611320 # ITB hits
system.cpu.itb.fetch_misses 44520 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 48655840 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 215 # Number of system calls
system.cpu.numCycles 279850922 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 29230505 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 24259169 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 280386575 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 159335859 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 439722434 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 119631955 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 100196481 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 219828436 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 100484573 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 168485322 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 14315634 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 833366 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 15149000 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 29438551 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.975851 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 205475782 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 2124323 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 279400656 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7212 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 13544259 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 266306663 # Number of cycles cpu stages are processed.
system.cpu.activity 95.160188 # Percentage of cycles cpu is active
system.cpu.comLoads 94754489 # Number of Load instructions committed
system.cpu.comStores 73520729 # Number of Store instructions committed
system.cpu.comBranches 44587532 # Number of Branches instructions committed
system.cpu.comNops 23089775 # Number of Nop instructions committed
system.cpu.comNonSpec 215 # Number of Non-Speculative instructions committed
system.cpu.comInts 112239074 # Number of Integer instructions committed
system.cpu.comFloats 50439198 # Number of Floating Point instructions committed
system.cpu.committedInsts 398664595 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 398664595 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 398664595 # Number of Instructions committed (Total)
system.cpu.cpi 0.701971 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.701971 # CPI: Total CPI of All Threads
system.cpu.ipc 1.424561 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.424561 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 78103252 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 201747670 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 72.091122 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 107199191 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 172651731 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 61.694180 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 102635700 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 177215222 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 63.324866 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 181106302 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 98744620 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 35.284722 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 90382943 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 189467979 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 67.703182 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 1975 # number of replacements
system.cpu.icache.tags.tagsinuse 1830.939956 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 48606789 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 3903 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 12453.699462 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1830.939956 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.894014 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.894014 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1928 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 108 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 322 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 1366 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.941406 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 97226543 # Number of tag accesses
system.cpu.icache.tags.data_accesses 97226543 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 48606789 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 48606789 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 48606789 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 48606789 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 48606789 # number of overall hits
system.cpu.icache.overall_hits::total 48606789 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 4531 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 4531 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 4531 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 4531 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 4531 # number of overall misses
system.cpu.icache.overall_misses::total 4531 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 279235250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 279235250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 279235250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 279235250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 279235250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 279235250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 48611320 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 48611320 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 48611320 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 48611320 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 48611320 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 48611320 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000093 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000093 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000093 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000093 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000093 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61627.731185 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 61627.731185 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 61627.731185 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 61627.731185 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 61627.731185 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 330 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 3 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 110 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 628 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 628 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 628 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 628 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 628 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 628 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 3903 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 3903 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 3903 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 3903 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 3903 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 243851250 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 243851250 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 243851250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 243851250 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 243851250 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 243851250 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000080 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000080 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000080 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 62477.901614 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 62477.901614 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 62477.901614 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 62477.901614 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 3981091 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 4850 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 4850 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 649 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 3205 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 3205 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 7806 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8953 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 16759 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 249792 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 307264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 557056 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 557056 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 5001000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 6455750 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 6676249 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 3906.848534 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 753 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 4717 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.159635 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 370.535307 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2908.741321 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 627.571906 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.011308 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.088768 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.019152 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.119228 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 4717 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 127 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 98 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 564 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 3928 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.143951 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 77554 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 77554 # Number of data accesses
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system.cpu.l2cache.ReadReq_hits::cpu.data 123 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 667 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 649 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 649 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 60 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 60 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 544 # number of demand (read+write) hits
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system.cpu.l2cache.demand_hits::total 727 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 544 # number of overall hits
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system.cpu.l2cache.overall_hits::total 727 # number of overall hits
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system.cpu.l2cache.Writeback_accesses::writebacks 649 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 649 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.ReadExReq_avg_miss_latency::total 73738.235294 # average ReadExReq miss latency
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system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 69801.205716 # average overall miss latency
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system.cpu.l2cache.overall_avg_miss_latency::total 71884.074782 # average overall miss latency
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system.cpu.l2cache.fast_writes 0 # number of fast writes performed
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system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency
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system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57270.690682 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61258.944318 # average overall mshr miss latency
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system.cpu.dcache.tags.replacements 764 # number of replacements
system.cpu.dcache.tags.tagsinuse 3284.892778 # Cycle average of tags in use
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system.cpu.dcache.tags.age_task_id_blocks_1024::4 3109 # Occupied blocks per task id
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system.cpu.dcache.ReadReq_mshr_miss_latency::total 62852251 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 235649500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 235649500 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 298501751 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 298501751 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 298501751 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 298501751 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000010 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000044 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000025 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000025 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66160.264211 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66160.264211 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 73594.472205 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 73594.472205 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 71893.485308 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 71893.485308 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

346
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -1,346 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=vortex lendian.raw
cwd=build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/vortex
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

5
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,5 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

11
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,11 +0,0 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 16:27:55
gem5 started Jan 22 2014 18:16:43
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/50.vortex/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Exiting @ tick 43690025000 because target called exit()

158
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.msg
View file

@ -1,158 +0,0 @@
SYSTEM TYPE...
__ZTC__ := False
__UNIX__ := True
__RISC__ := True
SPEC_CPU2000_LP64 := True
__MAC__ := False
__BCC__ := False
__BORLANDC__ := False
__GUI__ := False
__WTC__ := False
__HP__ := False
CODE OPTIONS...
__MACROIZE_HM__ := True
__MACROIZE_MEM__ := True
ENV01 := True
USE_HPP_STYPE_HDRS := False
USE_H_STYPE_HDRS := False
CODE INCLUSION PARAMETERS...
INCLUDE_ALL_CODE := False
INCLUDE_DELETE_CODE := True
__SWAP_GRP_POS__ := True
__INCLUDE_MTRX__ := False
__BAD_CODE__ := False
API_INCLUDE := False
BE_CAREFUL := False
OLDWAY := False
NOTUSED := False
SYSTEM PARAMETERS...
EXT_ENUM := 999999999L
CHUNK_CONSTANT := 55555555
CORE_CONSTANT := 55555555
CORE_LIMIT := 20971520
CorePage_Size := 384000
ALIGN_BYTES := True
CORE_BLOCK_ALIGN := 8
FAR_MEM := False
MEMORY MANAGEMENT PARAMETERS...
SYSTEM_ALLOC := True
SYSTEM_FREESTORE := True
__NO_DISKCACHE__ := False
__FREEZE_VCHUNKS__ := True
__FREEZE_GRP_PACKETS__ := True
__MINIMIZE_TREE_CACHE__:= True
SYSTEM STD PARAMETERS...
__STDOUT__ := False
NULL := 0
LPTR := False
False_Status := 1
True_Status := 0
LARGE := True
TWOBYTE_BOOL := False
__NOSTR__ := False
MEMORY VALIDATION PARAMETERS...
CORE_CRC_CHECK := False
VALIDATE_MEM_CHUNKS := False
SYSTEM DEBUG OPTIONS...
DEBUG := False
MCSTAT := False
TRACKBACK := False
FLUSH_FILES := False
DEBUG_CORE0 := False
DEBUG_RISC := False
__TREE_BUG__ := False
__TRACK_FILE_READS__ := False
PAGE_SPACE := False
LEAVE_NO_TRACE := True
NULL_TRACE_STRS := False
TIME PARAMETERS...
CLOCK_IS_LONG := False
__DISPLAY_TIME__ := False
__TREE_TIME__ := False
__DISPLAY_ERRORS__ := False
API MACROS...
__BMT01__ := True
OPTIMIZE := True
END OF DEFINES.
... IMPLODE MEMORY ...
SWAP to DiskCache := False
FREEZE_GRP_PACKETS:= True
QueBug := 1000
sizeof(boolean) = 4
sizeof(sizetype) = 4
sizeof(chunkstruc) = 32
sizeof(shorttype ) = 2
sizeof(idtype ) = 2
sizeof(sizetype ) = 4
sizeof(indextype ) = 4
sizeof(numtype ) = 4
sizeof(handletype) = 4
sizeof(tokentype ) = 8
sizeof(short ) = 2
sizeof(int ) = 4
sizeof(lt64 ) = 4
sizeof(farlongtype) = 4
sizeof(long ) = 8
sizeof(longaddr ) = 8
sizeof(float ) = 4
sizeof(double ) = 8
sizeof(addrtype ) = 8
sizeof(char * ) = 8
ALLOC CORE_1 :: 16
BHOOLE NATH
OPEN File ./input/lendian.rnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 2030c0
DB BlkDirChunk : Chunk[ 10] AT Vbn[3146]
DB BlkTknChunk : Chunk[ 11] AT Vbn[3147]
DB BlkSizeChunk : Chunk[ 12] AT Vbn[3148]
DB Handle Chunk's StackPtr = 20797
DB[ 1] LOADED; Handles= 20797
KERNEL in CORE[ 1] Restored @ 4005c800
OPEN File ./input/lendian.wnv
*Status = 0
DB HDR restored from FileVbn[ 0]
DB BlkDirOffset : @ 21c40
DB BlkDirChunk : Chunk[ 31] AT Vbn[ 81]
DB BlkTknChunk : Chunk[ 32] AT Vbn[ 82]
DB BlkSizeChunk : Chunk[ 33] AT Vbn[ 83]
DB Handle Chunk's StackPtr = 17
DB[ 2] LOADED; Handles= 17
VORTEx_Status == -8 || fffffff8
BE HERE NOW !!!
... VORTEx ON LINE ...
... END OF SESSION ...

258
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/smred.out
View file

@ -1,258 +0,0 @@
CREATE Db Header and Db Primal ...
NEW DB [ 3] Created.
VORTEX INPUT PARAMETERS::
MESSAGE FileName: smred.msg
OUTPUT FileName: smred.out
DISK CACHE FileName: NULL
PART DB FileName: parts.db
DRAW DB FileName: draw.db
PERSON DB FileName: emp.db
PERSONS Data FileName: ./input/persons.250
PARTS Count : 100
OUTER Loops : 1
INNER Loops : 1
LOOKUP Parts : 25
DELETE Parts : 10
STUFF Parts : 10
DEPTH Traverse: 5
% DECREASE Parts : 0
% INCREASE LookUps : 0
% INCREASE Deletes : 0
% INCREASE Stuffs : 0
FREEZE_PACKETS : 1
ALLOC_CHUNKS : 10000
EXTEND_CHUNKS : 5000
DELETE Draw objects : True
DELETE Part objects : False
QUE_BUG : 1000
VOID_BOUNDARY : 67108864
VOID_RESERVE : 1048576
COMMIT_DBS : False
BMT TEST :: files...
EdbName := PartLib
EdbFileName := parts.db
DrwName := DrawLib
DrwFileName := draw.db
EmpName := PersonLib
EmpFileName := emp.db
Swap to DiskCache := False
Freeze the cache := True
BMT TEST :: parms...
DeBug modulo := 1000
Create Parts count:= 100
Outer Loops := 1
Inner Loops := 1
Look Ups := 25
Delete Parts := 10
Stuff Parts := 10
Traverse Limit := 5
Delete Draws := True
Delete Parts := False
Delete ALL Parts := after every <mod 0>Outer Loop
INITIALIZE LIBRARY ::
INITIALIZE SCHEMA ::
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 4] Created.
PartLibCreate:: Db[ 4]; VpartsDir= 1
Part Count= 1
Initialize the Class maps
LIST HEADS loaded ... DbListHead_Class = 207
DbListNode_Class = 206
...NOTE... ShellLoadCode:: Class[ 228] will NOT be Activated.
...NOTE... ShellLoadCode:: Class[ 229] will NOT be Activated.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 5] Created.
DrawLibCreate:: Db[ 5]; VpartsDir= 1
Initialize the Class maps of this schema.
Primal_CreateDb Accessed !!!
CREATE Db Header and Db Primal ...
NEW DB [ 6] Created.
***NOTE*** Persons Library Extended!
Create <131072> Persons.
ItNum 0. Person[ 6: 5]. Name= Riddell , Robert V. ;
LAST Person Read::
ItNum 250. Person[ 6: 503]. Name= Gonzales , Warren X. ;
BUILD <Query0> for <Part2> class::
if (link[1].length >= 5) ::
Build Query2 for <Address> class::
if (State == CA || State == T*)
Build Query1 for <Person> class::
if (LastName >= H* && LastName <= P* && Query0(Residence)) ::
BUILD <Query3> for <DrawObj> class::
if (Id >= 3000
&& (Id >= 3000 && Id <= 3001)
&& Id >= 3002)
BUILD <Query4> for <NamedDrawObj> class::
if (Nam == Pre*
|| (Nam == ??Mid??? || == Pre??Mid?? || == ??Post
|| == Pre??Post || == ??Mid???Post || == Pre??Mid???Post)
&& Id <= 7)
SEED := 1008; Swap = False; RgnEntries = 135
OUTER LOOP [ 1] : NewParts = 100 LookUps = 25 StuffParts = 10.
Create 100 New Parts
Create Part 1. Token[ 4: 2].
< 100> Parts Created. CurrentId= 100
Connect each instantiated Part TO 3 unique Parts
Connect Part 1. Token[ 4: 2]
Connect Part 25. Token[ 4: 26] FromList= 26.
Connect Part 12. Token[ 4: 13] FromList= 13.
Connect Part 59. Token[ 4: 60] FromList= 60.
SET <DrawObjs> entries::
1. [ 5: 5] := <1 >; @[: 6]
Iteration count = 100
SET <NamedDrawObjs> entries::
1. [ 5: 39] := <14 >;
Iteration count = 12
SET <LibRectangles> entries::
1. [ 5: 23] := <8 >; @[: 24]
Iteration count = 12
LIST <DbRectangles> entries::
1. [ 5: 23]
Iteration count = 12
SET <PersonNames > entries::
Iteration count = 250
COMMIT All Image copies:: Release=<True>; Max Parts= 100
< 100> Part images' Committed.
< 0> are Named.
< 50> Point images' Committed.
< 81> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. TestObj Committed.
< 0> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 0: 0]. CartesianPoint Committed.
< 0> CartesianPoint images' Committed.
BEGIN Inner Loop Sequence::.
INNER LOOP [ 1: 1] :
LOOK UP 25 Random Parts and Export each Part.
LookUp for 26 parts; Asserts = 8
<Part2 > Asserts = 2; NULL Asserts = 3.
<DrawObj > Asserts = 0; NULL Asserts = 5.
<NamedObj > Asserts = 0; NULL Asserts = 0.
<Person > Asserts = 0; NULL Asserts = 5.
<TestObj > Asserts = 60; NULL Asserts = 0.
DELETE 10 Random Parts.
PartDelete :: Token[ 4: 91].
PartDisconnect:: Token[ 4: 91] id:= 90 for each link.
DisConnect link [ 0]:= 50; PartToken[ 51: 51].
DisConnect link [ 1]:= 17; PartToken[ 18: 18].
DisConnect link [ 2]:= 72; PartToken[ 73: 73].
DeleteFromList:: Vchunk[ 4: 91]. (* 1)
DisConnect FromList[ 0]:= 56; Token[ 57: 57].
Vlists[ 89] := 100;
Delete for 11 parts;
Traverse Count= 0
TRAVERSE PartId[ 6] and all Connections to 5 Levels
SEED In Traverse Part [ 4: 65] @ Level = 4.
Traverse Count= 357
Traverse Asserts = 5. True Tests = 1
< 5> DrawObj objects DELETED.
< 2> are Named.
< 2> Point objects DELETED.
CREATE 10 Additional Parts
Create 10 New Parts
Create Part 101. Token[ 4: 102].
< 10> Parts Created. CurrentId= 110
Connect each instantiated Part TO 3 unique Parts
COMMIT All Image copies:: Release=<True>; Max Parts= 110
< 81> Part images' Committed.
< 0> are Named.
< 38> Point images' Committed.
< 31> Person images' Committed.
COMMIT Parts(* 100)
Commit TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Committed.
< 15> TestObj images' Committed.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Committed.
< 16> CartesianPoint images' Committed.
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
ItNum 0. Token[ 3: 4]. TestObj Deleted.
< 15> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
ItNum 0. Token[ 3: 3]. CartesianPoint Deleted.
< 16> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
END INNER LOOP [ 1: 1].
DELETE All TestObj objects;
Delete TestObj_Class in <Primal> DB.
< 0> TestObj objects Deleted.
Commit CartesianPoint_Class in <Primal> DB.
< 0> CartesianPoint objects Deleted.
DELETE TestObj and Point objects...
STATUS= -201
V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!V O R T E x 0 1!

754
tests/long/se/50.vortex/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,754 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.043473 # Number of seconds simulated
sim_ticks 43472869000 # Number of ticks simulated
final_tick 43472869000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 112027 # Simulator instruction rate (inst/s)
host_op_rate 112027 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 55129043 # Simulator tick rate (ticks/s)
host_mem_usage 274568 # Number of bytes of host memory used
host_seconds 788.57 # Real time elapsed on the host
sim_insts 88340673 # Number of instructions simulated
sim_ops 88340673 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 454592 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10138368 # Number of bytes read from this memory
system.physmem.bytes_read::total 10592960 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 454592 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 454592 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 7295808 # Number of bytes written to this memory
system.physmem.bytes_written::total 7295808 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 7103 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 158412 # Number of read requests responded to by this memory
system.physmem.num_reads::total 165515 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 113997 # Number of write requests responded to by this memory
system.physmem.num_writes::total 113997 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 10456913 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 233211385 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 243668298 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 10456913 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 10456913 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 167824396 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 167824396 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 167824396 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 10456913 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 233211385 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 411492694 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 165515 # Number of read requests accepted
system.physmem.writeReqs 113997 # Number of write requests accepted
system.physmem.readBursts 165515 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 113997 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 10592320 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 640 # Total number of bytes read from write queue
system.physmem.bytesWritten 7293824 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 10592960 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 7295808 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 10 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 10379 # Per bank write bursts
system.physmem.perBankRdBursts::1 10436 # Per bank write bursts
system.physmem.perBankRdBursts::2 10256 # Per bank write bursts
system.physmem.perBankRdBursts::3 10015 # Per bank write bursts
system.physmem.perBankRdBursts::4 10350 # Per bank write bursts
system.physmem.perBankRdBursts::5 10362 # Per bank write bursts
system.physmem.perBankRdBursts::6 9796 # Per bank write bursts
system.physmem.perBankRdBursts::7 10273 # Per bank write bursts
system.physmem.perBankRdBursts::8 10509 # Per bank write bursts
system.physmem.perBankRdBursts::9 10590 # Per bank write bursts
system.physmem.perBankRdBursts::10 10475 # Per bank write bursts
system.physmem.perBankRdBursts::11 10188 # Per bank write bursts
system.physmem.perBankRdBursts::12 10235 # Per bank write bursts
system.physmem.perBankRdBursts::13 10580 # Per bank write bursts
system.physmem.perBankRdBursts::14 10468 # Per bank write bursts
system.physmem.perBankRdBursts::15 10593 # Per bank write bursts
system.physmem.perBankWrBursts::0 7081 # Per bank write bursts
system.physmem.perBankWrBursts::1 7259 # Per bank write bursts
system.physmem.perBankWrBursts::2 7255 # Per bank write bursts
system.physmem.perBankWrBursts::3 6998 # Per bank write bursts
system.physmem.perBankWrBursts::4 7125 # Per bank write bursts
system.physmem.perBankWrBursts::5 7170 # Per bank write bursts
system.physmem.perBankWrBursts::6 6769 # Per bank write bursts
system.physmem.perBankWrBursts::7 7083 # Per bank write bursts
system.physmem.perBankWrBursts::8 7217 # Per bank write bursts
system.physmem.perBankWrBursts::9 6938 # Per bank write bursts
system.physmem.perBankWrBursts::10 7081 # Per bank write bursts
system.physmem.perBankWrBursts::11 6989 # Per bank write bursts
system.physmem.perBankWrBursts::12 6963 # Per bank write bursts
system.physmem.perBankWrBursts::13 7284 # Per bank write bursts
system.physmem.perBankWrBursts::14 7282 # Per bank write bursts
system.physmem.perBankWrBursts::15 7472 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 43472848000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 165515 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 113997 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 70302 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 51581 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 34122 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 9498 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 2 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 954 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 997 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 2155 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 2833 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 4913 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 6026 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 6448 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 6697 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 6974 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 7338 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 7765 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 8182 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 8823 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 9350 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 8420 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 8642 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 8524 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 8027 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 402 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 219 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 140 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 120 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 25 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 4 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 3 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 52007 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 343.898321 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 202.122220 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 343.471226 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 18183 34.96% 34.96% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 10752 20.67% 55.64% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 5531 10.64% 66.27% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 3167 6.09% 72.36% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 2729 5.25% 77.61% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 1801 3.46% 81.07% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 1676 3.22% 84.29% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 1325 2.55% 86.84% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 6843 13.16% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 52007 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 6952 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 23.806818 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 349.983272 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 6951 99.99% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::28672-29695 1 0.01% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 6952 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 6951 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 16.395339 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 16.363988 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.079809 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 5950 85.60% 85.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 35 0.50% 86.10% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 555 7.98% 94.09% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 213 3.06% 97.15% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 101 1.45% 98.60% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 56 0.81% 99.41% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 23 0.33% 99.74% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 12 0.17% 99.91% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 2 0.03% 99.94% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 2 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 1 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::30 1 0.01% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 6951 # Writes before turning the bus around for reads
system.physmem.totQLat 4829573500 # Total ticks spent queuing
system.physmem.totMemAccLat 7932792250 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 827525000 # Total ticks spent in databus transfers
system.physmem.avgQLat 29180.83 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 47930.83 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 243.65 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 167.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 243.67 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 167.82 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 3.21 # Data bus utilization in percentage
system.physmem.busUtilRead 1.90 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 1.31 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.47 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.54 # Average write queue length when enqueuing
system.physmem.readRowHits 145183 # Number of row buffer hits during reads
system.physmem.writeRowHits 82273 # Number of row buffer hits during writes
system.physmem.readRowHitRate 87.72 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 72.17 # Row buffer hit rate for writes
system.physmem.avgGap 155531.24 # Average gap between requests
system.physmem.pageHitRate 81.38 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 26086323250 # Time in different power states
system.physmem.memoryStateTime::REF 1451580000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 15933004250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 411492694 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 34625 # Transaction distribution
system.membus.trans_dist::ReadResp 34625 # Transaction distribution
system.membus.trans_dist::Writeback 113997 # Transaction distribution
system.membus.trans_dist::ReadExReq 130890 # Transaction distribution
system.membus.trans_dist::ReadExResp 130890 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 445027 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 445027 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 17888768 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 17888768 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 17888768 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 1219071000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
system.membus.respLayer1.occupancy 1523545750 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 3.5 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 18742718 # Number of BP lookups
system.cpu.branchPred.condPredicted 12318358 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4775680 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 15507357 # Number of BTB lookups
system.cpu.branchPred.BTBHits 4664025 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 30.076208 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1660965 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 1030 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 20277728 # DTB read hits
system.cpu.dtb.read_misses 90148 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 20367876 # DTB read accesses
system.cpu.dtb.write_hits 14728971 # DTB write hits
system.cpu.dtb.write_misses 7252 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 14736223 # DTB write accesses
system.cpu.dtb.data_hits 35006699 # DTB hits
system.cpu.dtb.data_misses 97400 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 35104099 # DTB accesses
system.cpu.itb.fetch_hits 12367762 # ITB hits
system.cpu.itb.fetch_misses 11021 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 12378783 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 4583 # Number of system calls
system.cpu.numCycles 86945739 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 8074236 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 10668482 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 74162124 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 52319250 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 126481374 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 66044 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 227630 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 293674 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 14174248 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 35060070 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 4449011 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 216169 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4665180 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 9107422 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 33.872902 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 44777931 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 41107 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 77212885 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 241035 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 17370075 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 69575664 # Number of cycles cpu stages are processed.
system.cpu.activity 80.021936 # Percentage of cycles cpu is active
system.cpu.comLoads 20276638 # Number of Load instructions committed
system.cpu.comStores 14613377 # Number of Store instructions committed
system.cpu.comBranches 13754477 # Number of Branches instructions committed
system.cpu.comNops 8748916 # Number of Nop instructions committed
system.cpu.comNonSpec 4583 # Number of Non-Speculative instructions committed
system.cpu.comInts 30791227 # Number of Integer instructions committed
system.cpu.comFloats 151453 # Number of Floating Point instructions committed
system.cpu.committedInsts 88340673 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 88340673 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 88340673 # Number of Instructions committed (Total)
system.cpu.cpi 0.984210 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.984210 # CPI: Total CPI of All Threads
system.cpu.ipc 1.016044 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.016044 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 34290146 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 52655593 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 60.561442 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 44490597 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 42455142 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 48.829468 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 43915285 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 43030454 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 49.491159 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 64825125 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 22120614 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 25.441861 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 40903528 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 46042211 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 52.955109 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 84371 # number of replacements
system.cpu.icache.tags.tagsinuse 1906.099937 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 12250492 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 86417 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 141.760209 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1906.099937 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.930713 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.930713 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 2046 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 62 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 1090 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 790 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.999023 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 24821923 # Number of tag accesses
system.cpu.icache.tags.data_accesses 24821923 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 12250492 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 12250492 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 12250492 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 12250492 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 12250492 # number of overall hits
system.cpu.icache.overall_hits::total 12250492 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 117261 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 117261 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 117261 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 117261 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 117261 # number of overall misses
system.cpu.icache.overall_misses::total 117261 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 1989588981 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 1989588981 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 1989588981 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 1989588981 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 1989588981 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 1989588981 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 12367753 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 12367753 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 12367753 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 12367753 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 12367753 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 12367753 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.009481 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.009481 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.009481 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.009481 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.009481 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.009481 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 16967.184153 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 16967.184153 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 16967.184153 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 16967.184153 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 16967.184153 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 347 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 192 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 15 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 4 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 23.133333 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 48 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 30844 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 30844 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 30844 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 30844 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 30844 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 30844 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 86417 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 86417 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 86417 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 86417 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 86417 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 86417 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 1409598264 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 1409598264 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 1409598264 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 1409598264 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 1409598264 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 1409598264 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.006987 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.006987 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.006987 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.006987 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 16311.585267 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 16311.585267 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 16311.585267 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 16311.585267 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 675902573 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 146995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 146995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 168352 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 143769 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 143769 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 172834 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 577046 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 749880 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 5530688 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 23852736 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 29383424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 29383424 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 397910000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 130854736 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.3 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 326587968 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.8 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 131591 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30879.620467 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 151434 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 163651 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.925347 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 27087.517417 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 2008.809532 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 1783.293518 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.826645 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.061304 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.054422 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.942371 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 32060 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 144 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 1167 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 17062 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 13579 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 108 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.978394 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 3980348 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 3980348 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 79314 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 33056 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 112370 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 168352 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 168352 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 12879 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 12879 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 79314 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 45935 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 125249 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 79314 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 45935 # number of overall hits
system.cpu.l2cache.overall_hits::total 125249 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 7103 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 27522 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 34625 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 130890 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 130890 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 7103 # number of demand (read+write) misses
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system.cpu.l2cache.overall_misses::cpu.inst 7103 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 158412 # number of overall misses
system.cpu.l2cache.overall_misses::total 165515 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 527407000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 2000529000 # number of ReadReq miss cycles
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system.cpu.l2cache.ReadExReq_miss_latency::total 12857601250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 527407000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 14858130250 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 15385537250 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 527407000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 14858130250 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 15385537250 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 86417 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 60578 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 146995 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 168352 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 168352 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 143769 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 143769 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 86417 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 204347 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 290764 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 86417 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 204347 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 290764 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.082194 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.454323 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.235552 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.910419 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.910419 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.082194 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.775211 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.569242 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.082194 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.775211 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.569242 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 74251.302267 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 72688.358404 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 73008.981949 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 98232.112843 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 98232.112843 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 92955.546325 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 74251.302267 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 93794.221713 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 92955.546325 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 113997 # number of writebacks
system.cpu.l2cache.writebacks::total 113997 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 7103 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 27522 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 34625 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 130890 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 130890 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 7103 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 158412 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 165515 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 7103 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 158412 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 165515 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 438280000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 1653149000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 2091429000 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 11252735250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 11252735250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 438280000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 12905884250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 13344164250 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 438280000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 12905884250 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 13344164250 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.454323 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.235552 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.910419 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.910419 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.569242 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.082194 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.775211 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.569242 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 61703.505561 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 60066.455926 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60402.281588 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 85970.931698 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 85970.931698 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 61703.505561 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81470.369985 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 80622.084101 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 200251 # number of replacements
system.cpu.dcache.tags.tagsinuse 4076.191917 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 33755204 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 204347 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 165.185709 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 301118000 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4076.191917 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.995164 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.995164 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 64 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 933 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 3099 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 69984377 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 69984377 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 20180307 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 20180307 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 13574897 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 13574897 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 33755204 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 33755204 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 33755204 # number of overall hits
system.cpu.dcache.overall_hits::total 33755204 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 96331 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 96331 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 1038480 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 1038480 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 1134811 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 1134811 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 1134811 # number of overall misses
system.cpu.dcache.overall_misses::total 1134811 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 5018382484 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 5018382484 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 82442485122 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 82442485122 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 87460867606 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 87460867606 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 87460867606 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 87460867606 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 20276638 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 14613377 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 34890015 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 34890015 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 34890015 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 34890015 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.004751 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.004751 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.071064 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.071064 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.032525 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.032525 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.032525 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.032525 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52095.197641 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 52095.197641 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79387.648411 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 79387.648411 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 77070.866960 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 77070.866960 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 77070.866960 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 5473044 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 77 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 116736 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 46.883943 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 77 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 168352 # number of writebacks
system.cpu.dcache.writebacks::total 168352 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 35564 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 35564 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 894900 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 894900 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 930464 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 930464 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 930464 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 930464 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 60767 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 60767 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 143580 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 143580 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 204347 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 204347 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 204347 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 2395231766 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 2395231766 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 13128048266 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 13128048266 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 15523280032 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 15523280032 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 15523280032 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 15523280032 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002997 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009825 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.005857 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.005857 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 39416.653216 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 39416.653216 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 91433.683424 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 91433.683424 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 75965.294484 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 75965.294484 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

346
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -1,346 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=bzip2 input.source 1
cwd=build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/bzip2
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

5
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,5 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(18446744073709547831, 1, ...)

26
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,26 +0,0 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 16:27:55
gem5 started Jan 22 2014 18:29:41
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/60.bzip2/alpha/tru64/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
info: Increasing stack size by one page.
spec_init
Loading Input Data
Input data 1048576 bytes in length
Compressing Input Data, level 7
Compressed data 198546 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Compressing Input Data, level 9
Compressed data 198677 bytes in length
Uncompressing Data
Uncompressed data 1048576 bytes in length
Uncompressed data compared correctly
Tested 1MB buffer: OK!
Exiting @ tick 1009838214500 because target called exit()

761
tests/long/se/60.bzip2/ref/alpha/tru64/inorder-timing/stats.txt
View file

@ -1,761 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 1.005768 # Number of seconds simulated
sim_ticks 1005767806500 # Number of ticks simulated
final_tick 1005767806500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 106626 # Simulator instruction rate (inst/s)
host_op_rate 106626 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 58930745 # Simulator tick rate (ticks/s)
host_mem_usage 266468 # Number of bytes of host memory used
host_seconds 17066.95 # Real time elapsed on the host
sim_insts 1819780127 # Number of instructions simulated
sim_ops 1819780127 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 54976 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 125365120 # Number of bytes read from this memory
system.physmem.bytes_read::total 125420096 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 54976 # Number of instructions bytes read from this memory
system.physmem.bytes_written::writebacks 65155584 # Number of bytes written to this memory
system.physmem.bytes_written::total 65155584 # Number of bytes written to this memory
system.physmem.num_reads::cpu.inst 859 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 1958830 # Number of read requests responded to by this memory
system.physmem.num_reads::total 1959689 # Number of read requests responded to by this memory
system.physmem.num_writes::writebacks 1018056 # Number of write requests responded to by this memory
system.physmem.num_writes::total 1018056 # Number of write requests responded to by this memory
system.physmem.bw_read::cpu.inst 54661 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 124646185 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 124700846 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 54661 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 54661 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_write::writebacks 64781934 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_write::total 64781934 # Write bandwidth from this memory (bytes/s)
system.physmem.bw_total::writebacks 64781934 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 54661 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 124646185 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 189482780 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 1959689 # Number of read requests accepted
system.physmem.writeReqs 1018056 # Number of write requests accepted
system.physmem.readBursts 1959689 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 1018056 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 125339392 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 80704 # Total number of bytes read from write queue
system.physmem.bytesWritten 65154112 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 125420096 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 65155584 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 1261 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 118688 # Per bank write bursts
system.physmem.perBankRdBursts::1 114039 # Per bank write bursts
system.physmem.perBankRdBursts::2 116164 # Per bank write bursts
system.physmem.perBankRdBursts::3 117666 # Per bank write bursts
system.physmem.perBankRdBursts::4 117733 # Per bank write bursts
system.physmem.perBankRdBursts::5 117466 # Per bank write bursts
system.physmem.perBankRdBursts::6 119809 # Per bank write bursts
system.physmem.perBankRdBursts::7 124448 # Per bank write bursts
system.physmem.perBankRdBursts::8 126913 # Per bank write bursts
system.physmem.perBankRdBursts::9 130015 # Per bank write bursts
system.physmem.perBankRdBursts::10 128579 # Per bank write bursts
system.physmem.perBankRdBursts::11 130223 # Per bank write bursts
system.physmem.perBankRdBursts::12 125906 # Per bank write bursts
system.physmem.perBankRdBursts::13 125163 # Per bank write bursts
system.physmem.perBankRdBursts::14 122509 # Per bank write bursts
system.physmem.perBankRdBursts::15 123107 # Per bank write bursts
system.physmem.perBankWrBursts::0 61223 # Per bank write bursts
system.physmem.perBankWrBursts::1 61467 # Per bank write bursts
system.physmem.perBankWrBursts::2 60558 # Per bank write bursts
system.physmem.perBankWrBursts::3 61216 # Per bank write bursts
system.physmem.perBankWrBursts::4 61647 # Per bank write bursts
system.physmem.perBankWrBursts::5 63085 # Per bank write bursts
system.physmem.perBankWrBursts::6 64137 # Per bank write bursts
system.physmem.perBankWrBursts::7 65614 # Per bank write bursts
system.physmem.perBankWrBursts::8 65332 # Per bank write bursts
system.physmem.perBankWrBursts::9 65770 # Per bank write bursts
system.physmem.perBankWrBursts::10 65297 # Per bank write bursts
system.physmem.perBankWrBursts::11 65611 # Per bank write bursts
system.physmem.perBankWrBursts::12 64139 # Per bank write bursts
system.physmem.perBankWrBursts::13 64200 # Per bank write bursts
system.physmem.perBankWrBursts::14 64551 # Per bank write bursts
system.physmem.perBankWrBursts::15 64186 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 1005767733500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 1959689 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 1018056 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 1667897 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 193105 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 75870 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 21555 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 1 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 29926 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 31516 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 51008 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 56043 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 59405 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 60493 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 60664 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 60587 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 60540 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 60592 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 60684 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 60779 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 62031 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 62029 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 60742 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 61437 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 59898 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 59460 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 159 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 42 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 6 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 1810756 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 105.200206 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 81.912098 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 131.997170 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 1417049 78.26% 78.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 275870 15.24% 93.49% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 50109 2.77% 96.26% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 20785 1.15% 97.41% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 12643 0.70% 98.11% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 6844 0.38% 98.48% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 5544 0.31% 98.79% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 3818 0.21% 99.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 18094 1.00% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 1810756 # Bytes accessed per row activation
system.physmem.rdPerTurnAround::samples 59345 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::mean 32.999023 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::stdev 160.520477 # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::0-1023 59305 99.93% 99.93% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::1024-2047 12 0.02% 99.95% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::2048-3071 9 0.02% 99.97% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::3072-4095 9 0.02% 99.98% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::4096-5119 3 0.01% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::5120-6143 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::6144-7167 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::8192-9215 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::9216-10239 1 0.00% 99.99% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::12288-13311 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::16384-17407 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::19456-20479 1 0.00% 100.00% # Reads before turning the bus around for writes
system.physmem.rdPerTurnAround::total 59345 # Reads before turning the bus around for writes
system.physmem.wrPerTurnAround::samples 59345 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::mean 17.154486 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::gmean 17.116028 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::stdev 1.157894 # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::16 27533 46.39% 46.39% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::17 1478 2.49% 48.89% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::18 25288 42.61% 91.50% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::19 4106 6.92% 98.42% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::20 708 1.19% 99.61% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::21 151 0.25% 99.86% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::22 51 0.09% 99.95% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::23 15 0.03% 99.97% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::24 6 0.01% 99.98% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::25 2 0.00% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::26 4 0.01% 99.99% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::28 2 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::29 1 0.00% 100.00% # Writes before turning the bus around for reads
system.physmem.wrPerTurnAround::total 59345 # Writes before turning the bus around for reads
system.physmem.totQLat 39644301500 # Total ticks spent queuing
system.physmem.totMemAccLat 76364826500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 9792140000 # Total ticks spent in databus transfers
system.physmem.avgQLat 20242.92 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 38992.92 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 124.62 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 64.78 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 124.70 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 64.78 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 1.48 # Data bus utilization in percentage
system.physmem.busUtilRead 0.97 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.51 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.04 # Average read queue length when enqueuing
system.physmem.avgWrQLen 24.55 # Average write queue length when enqueuing
system.physmem.readRowHits 749188 # Number of row buffer hits during reads
system.physmem.writeRowHits 416511 # Number of row buffer hits during writes
system.physmem.readRowHitRate 38.25 # Row buffer hit rate for reads
system.physmem.writeRowHitRate 40.91 # Row buffer hit rate for writes
system.physmem.avgGap 337761.54 # Average gap between requests
system.physmem.pageHitRate 39.16 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 297166155500 # Time in different power states
system.physmem.memoryStateTime::REF 33584720000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 675014883250 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 189482780 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 1178393 # Transaction distribution
system.membus.trans_dist::ReadResp 1178393 # Transaction distribution
system.membus.trans_dist::Writeback 1018056 # Transaction distribution
system.membus.trans_dist::ReadExReq 781296 # Transaction distribution
system.membus.trans_dist::ReadExResp 781296 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 4937434 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 4937434 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 190575680 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 190575680 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 190575680 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 11779296500 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 1.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 18345408000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 1.8 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 326515024 # Number of BP lookups
system.cpu.branchPred.condPredicted 252570896 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 138240520 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 220728385 # Number of BTB lookups
system.cpu.branchPred.BTBHits 135412850 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 61.348181 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 16767439 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 6 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 444825863 # DTB read hits
system.cpu.dtb.read_misses 4897078 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 449722941 # DTB read accesses
system.cpu.dtb.write_hits 160844247 # DTB write hits
system.cpu.dtb.write_misses 1701304 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 162545551 # DTB write accesses
system.cpu.dtb.data_hits 605670110 # DTB hits
system.cpu.dtb.data_misses 6598382 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 612268492 # DTB accesses
system.cpu.itb.fetch_hits 231919747 # ITB hits
system.cpu.itb.fetch_misses 22 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 231919769 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 29 # Number of system calls
system.cpu.numCycles 2011535614 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 172226277 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 154288747 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 1667639381 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 1376202617 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 3043841998 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 229 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 345 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 574 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 651725578 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 617883712 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 120527925 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 11114137 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 131642062 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 83557916 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.171968 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 1139358188 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 75 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 1742007028 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 7502506 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 439794636 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 1571740978 # Number of cycles cpu stages are processed.
system.cpu.activity 78.136373 # Percentage of cycles cpu is active
system.cpu.comLoads 444595663 # Number of Load instructions committed
system.cpu.comStores 160728502 # Number of Store instructions committed
system.cpu.comBranches 214632552 # Number of Branches instructions committed
system.cpu.comNops 83736345 # Number of Nop instructions committed
system.cpu.comNonSpec 29 # Number of Non-Speculative instructions committed
system.cpu.comInts 916086844 # Number of Integer instructions committed
system.cpu.comFloats 190 # Number of Floating Point instructions committed
system.cpu.committedInsts 1819780127 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 1819780127 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 1819780127 # Number of Instructions committed (Total)
system.cpu.cpi 1.105373 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 1.105373 # CPI: Total CPI of All Threads
system.cpu.ipc 0.904672 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.904672 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 824896841 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 1186638773 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 58.991686 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 1077691733 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 933843881 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 46.424427 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 1039140389 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 972395225 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 48.340940 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 1601912902 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 409622712 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 20.363682 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 990187341 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 1021348273 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 50.774556 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 1 # number of replacements
system.cpu.icache.tags.tagsinuse 668.237280 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 231918592 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 859 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 269986.719441 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 668.237280 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.326288 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.326288 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 858 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 73 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 785 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.418945 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 463840351 # Number of tag accesses
system.cpu.icache.tags.data_accesses 463840351 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 231918592 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 231918592 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 231918592 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 231918592 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 231918592 # number of overall hits
system.cpu.icache.overall_hits::total 231918592 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 1154 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 1154 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 1154 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 1154 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 1154 # number of overall misses
system.cpu.icache.overall_misses::total 1154 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 83508500 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 83508500 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 83508500 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 83508500 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 83508500 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 83508500 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 231919746 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 231919746 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 231919746 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 231919746 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 231919746 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 231919746 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.000005 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.000005 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.000005 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.000005 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.000005 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 72364.384749 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 72364.384749 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 72364.384749 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 72364.384749 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 72364.384749 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 162 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 418 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 1 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 162 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets 418 # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 295 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 295 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 295 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 295 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 295 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 295 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 859 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 859 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 859 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 61831500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 61831500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 61831500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 61831500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 61831500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 61831500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000004 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000004 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000004 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71980.791618 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71980.791618 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71980.791618 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 71980.791618 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 814858454 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 7222692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 7222692 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 3693285 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1889623 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1889623 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1718 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 21916197 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 21917915 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 54976 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 819503424 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 819558400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 819558400 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 10096085000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 1445000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 13977776250 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.4 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 1926959 # number of replacements
system.cpu.l2cache.tags.tagsinuse 30915.615811 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 8958694 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 1956752 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 4.578349 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 67887905750 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 14928.983043 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 34.785512 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 15951.847256 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.455596 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.001062 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.486812 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.943470 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 29793 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 158 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 592 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 746 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 12815 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15482 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.909210 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 106291175 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 106291175 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.data 6044299 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6044299 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 3693285 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 3693285 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 1108327 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 1108327 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.data 7152626 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 7152626 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.data 7152626 # number of overall hits
system.cpu.l2cache.overall_hits::total 7152626 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 859 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 1177534 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 1178393 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 781296 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 781296 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 859 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 1958830 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 1959689 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 859 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 1958830 # number of overall misses
system.cpu.l2cache.overall_misses::total 1959689 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 60968500 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 94791357750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 94852326250 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 65779017750 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 65779017750 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 60968500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 160570375500 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 160631344000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 60968500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 160570375500 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 160631344000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 859 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 7221833 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 7222692 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 3693285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 3693285 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 1889623 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 1889623 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 859 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 9111456 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 9112315 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 859 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 9111456 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 9112315 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.163052 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.163151 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.413467 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 0.413467 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 0.214985 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.215059 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 0.214985 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.215059 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70976.135041 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80499.890237 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 80492.947811 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 84192.185484 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 84192.185484 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 81967.773458 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70976.135041 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81972.593589 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 81967.773458 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.writebacks::writebacks 1018056 # number of writebacks
system.cpu.l2cache.writebacks::total 1018056 # number of writebacks
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 859 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 1177534 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 1178393 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 781296 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 781296 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 859 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 1958830 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 1959689 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 859 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 1958830 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 1959689 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 50186500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 80032548250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 80082734750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 56010972750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 56010972750 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 50186500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 136043521000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 136093707500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 50186500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 136043521000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 136093707500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.163052 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.163151 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.413467 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.413467 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.215059 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.214985 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.215059 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58424.330617 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67966.231336 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67959.275683 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71689.824023 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71689.824023 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58424.330617 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 69451.417938 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69446.584382 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 9107360 # number of replacements
system.cpu.dcache.tags.tagsinuse 4082.305318 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 593299863 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 9111456 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 65.115813 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 12706320250 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 4082.305318 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.996657 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.996657 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 574 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 2872 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 612 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 38 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 1219759786 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 1219759786 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 437268763 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 437268763 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 156031100 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 156031100 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 593299863 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 593299863 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 593299863 # number of overall hits
system.cpu.dcache.overall_hits::total 593299863 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 7326900 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 7326900 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 4697402 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 4697402 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 12024302 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 12024302 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 12024302 # number of overall misses
system.cpu.dcache.overall_misses::total 12024302 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 179720219500 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 179720219500 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 246249534250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 246249534250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 425969753750 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 425969753750 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 425969753750 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 425969753750 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 444595663 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 160728502 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 605324165 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 605324165 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 605324165 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 605324165 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.016480 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.016480 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.029226 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.029226 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.019864 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.019864 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.019864 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.019864 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 24528.821125 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 24528.821125 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 52422.495296 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 52422.495296 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 35425.736459 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 35425.736459 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 35425.736459 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 10235273 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 7848261 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 412771 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 73432 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 24.796492 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets 106.877941 # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 3693285 # number of writebacks
system.cpu.dcache.writebacks::total 3693285 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104626 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 104626 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 2808220 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 2808220 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 2912846 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 2912846 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 2912846 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 2912846 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 7222274 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 7222274 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1889182 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1889182 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 9111456 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 9111456 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 9111456 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 9111456 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 162584714500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 162584714500 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 78915202250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 78915202250 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 241499916750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 241499916750 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 241499916750 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 241499916750 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.016245 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.011754 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.015052 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.015052 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 22511.568309 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 22511.568309 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 41772.154430 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 41772.154430 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 26505.085109 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 26505.085109 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

346
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/config.ini
View file

@ -1,346 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=twolf smred
cwd=build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/dist/m5/cpu2000/binaries/alpha/tru64/twolf
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

5
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simerr
View file

@ -1,5 +0,0 @@
warn: Sockets disabled, not accepting gdb connections
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: Prefetch instructions in Alpha do not do anything
warn: ignoring syscall sigprocmask(1, ...)

26
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/simout
View file

@ -1,26 +0,0 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 16:27:55
gem5 started Jan 22 2014 19:03:25
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing -re tests/run.py build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sav
Couldn't unlink build/ALPHA/tests/opt/long/se/70.twolf/alpha/tru64/inorder-timing/smred.sv2
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
61 62 63 64 65 66 67 68 69 70 71 72 73 74 75
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
122 123 124 Exiting @ tick 41681685000 because target called exit()

276
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.out
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@ -1,276 +0,0 @@
TimberWolfSC version:v4.3a date:Mon Jan 25 18:50:36 EST 1988
Standard Cell Placement and Global Routing Program
Authors: Carl Sechen, Bill Swartz
Yale University
NOTE: Restart file .rs2 not used
TimberWolf will perform a global route step
rowSep: 1.000000
feedThruWidth: 4
******************
BLOCK DATA
block:1 desire:85
block:2 desire:85
Total Desired Length: 170
total cell length: 168
total block length: 168
block x-span:84 block y-span:78
implicit feed thru range: -84
Using default value of bin.penalty.control:1.000000
numBins automatically set to:5
binWidth = average_cell_width + 0 sigma= 17
average_cell_width is:16
standard deviation of cell length is:23.6305
TimberWolfSC starting from the beginning
THIS IS THE ROUTE COST OF THE ORIGINAL PLACEMENT: 645
The number of nets with 1 pin is 4
The number of nets with 2 pin is 9
The number of nets with 3 pin is 0
The number of nets with 4 pin is 2
The number of nets with 5 pin is 0
The number of nets with 6 pin is 0
The number of nets with 7 pin is 0
The number of nets with 8 pin is 0
The number of nets with 9 pin is 0
The number of nets with 10 pin or more is 0
New Cost Function: Initial Horizontal Cost:242
New Cost Function: FEEDS:0 MISSING_ROWS:-46
bdxlen:86 bdylen:78
l:0 t:78 r:86 b:0
THIS IS THE ROUTE COST OF THE CURRENT PLACEMENT: 645
THIS IS THE PENALTY OF THE CURRENT PLACEMENT: 44
The rand generator seed was at utemp() : 1
tempfile[0][0] = 0.982500 tempfile[0][1] = 90.000000
tempfile[1][0] = 0.915000 tempfile[1][1] = 20.000000
tempfile[2][0] = 0.700000 tempfile[2][1] = 10.000000
tempfile[3][0] = 0.100000 tempfile[3][1] = 0.000000
I T fds Wire Penalty P_lim Epct binC rowC acc s/p early FDs MRs
1 500 0 929 592 160 30.0 1.0 3.0 84.2 34.7 0.0 0 40
2 491 0 876 106 726 0.0 0.8 2.5 80.0 18.5 0.0 0 46
3 482 0 822 273 372 0.0 0.5 1.5 80.8 21.3 0.0 0 46
4 474 0 826 53 247 0.0 0.5 0.9 65.0 21.9 0.0 0 48
5 465 8 987 73 190 0.0 0.5 0.5 50.0 38.3 0.0 0 46
6 457 8 851 67 226 0.0 0.5 0.5 53.8 42.9 0.0 0 52
7 449 8 1067 108 190 0.0 0.5 0.5 46.2 53.8 0.0 0 50
8 441 8 918 106 171 0.0 0.5 0.5 47.1 40.4 0.0 0 48
9 434 8 812 101 197 0.0 0.5 0.5 53.6 21.0 0.0 0 48
10 426 8 1038 121 181 0.0 0.5 0.5 43.6 27.1 0.0 0 48
11 419 8 898 93 187 0.0 0.5 0.5 45.3 47.8 0.0 0 50
12 411 4 857 94 240 0.0 0.5 0.5 62.7 51.6 0.0 0 44
13 404 8 1043 88 185 0.0 0.5 0.5 54.0 52.8 0.0 0 50
14 397 8 767 94 154 0.0 0.5 0.5 33.8 35.0 0.0 0 50
15 390 8 862 89 183 0.0 0.5 0.5 55.6 29.0 0.0 0 46
16 383 4 798 79 173 0.0 0.5 0.5 57.5 35.3 0.0 0 52
17 376 8 827 100 152 0.0 0.5 0.5 35.3 81.8 0.0 0 50
18 370 8 878 101 208 0.0 0.5 0.5 44.7 46.2 0.0 0 48
19 363 4 921 67 167 0.0 0.5 0.5 57.1 34.7 0.0 0 48
20 357 8 933 93 154 0.0 0.5 0.5 46.5 43.6 0.0 0 52
21 351 8 930 89 147 0.0 0.5 0.5 39.4 36.5 0.0 0 52
22 345 8 951 79 142 0.0 0.5 0.5 32.8 51.3 0.0 0 50
23 339 8 1046 87 207 0.0 0.5 0.5 52.8 61.0 0.0 0 48
24 333 4 989 96 185 0.0 0.5 0.5 45.3 43.3 0.0 0 42
25 327 4 577 86 157 0.0 0.5 0.5 31.1 55.3 0.0 0 52
26 321 8 776 97 174 0.0 0.5 0.5 47.9 62.5 0.0 0 52
27 315 8 850 81 188 0.0 0.5 0.5 45.0 55.2 0.0 0 50
28 310 8 898 97 148 0.0 0.5 0.5 43.0 45.8 0.0 0 48
29 304 8 889 65 173 0.0 0.5 0.5 32.5 41.3 0.0 0 50
30 299 8 858 81 153 0.0 0.5 0.5 44.3 29.2 0.0 0 46
31 294 8 871 82 187 0.0 0.5 0.5 45.7 47.7 0.0 0 48
32 289 8 782 109 173 0.0 0.5 0.5 35.2 57.4 0.0 0 48
33 284 8 743 98 189 0.0 0.6 0.5 41.8 64.3 0.0 0 52
34 279 8 943 90 147 0.0 0.5 0.5 38.6 32.8 0.0 0 48
35 274 8 907 57 166 0.0 0.5 0.5 33.6 51.0 0.0 0 48
36 269 8 900 70 148 0.0 0.5 0.5 45.0 41.4 0.0 0 50
37 264 4 875 106 133 0.0 0.5 0.5 31.7 55.3 0.0 0 52
38 260 8 1023 145 149 0.0 0.6 0.5 28.7 65.0 0.0 0 52
39 255 8 801 151 173 0.0 0.9 0.5 41.7 41.2 0.0 0 48
40 251 8 741 104 159 0.0 0.8 0.5 36.3 47.5 0.0 0 48
41 246 8 828 108 149 0.0 0.5 0.5 34.6 50.9 0.0 0 50
42 242 8 947 128 132 0.0 0.7 0.5 34.2 39.0 0.0 0 50
43 238 8 917 101 142 0.0 0.8 0.5 34.4 50.9 0.0 0 48
44 234 8 761 86 129 0.0 0.5 0.5 42.0 36.4 0.0 0 52
45 229 8 979 106 137 0.0 0.5 0.5 29.2 55.3 0.0 0 50
46 225 8 806 74 130 0.0 0.7 0.5 33.1 65.4 0.0 0 52
47 221 8 971 125 114 0.0 0.5 0.5 31.9 45.6 0.0 0 52
48 218 8 869 125 104 0.0 0.9 0.5 30.0 56.0 0.0 0 48
49 214 8 999 153 140 0.0 0.8 0.5 30.4 46.4 0.0 0 52
50 210 8 798 192 139 0.0 1.0 0.5 28.9 50.0 0.0 0 52
51 206 8 860 125 157 0.0 1.2 0.5 31.5 26.9 0.0 0 52
52 203 8 893 186 127 5.9 0.9 0.5 26.4 42.3 0.0 0 46
53 199 8 863 126 141 0.0 1.2 0.5 32.5 44.4 0.0 0 44
54 196 8 788 97 133 0.0 0.9 0.5 37.5 40.0 0.0 0 50
55 192 8 926 119 116 0.0 0.6 0.5 26.1 55.3 0.0 0 52
56 189 8 789 162 107 0.0 0.8 0.5 25.2 40.4 0.0 0 48
57 186 8 878 107 128 0.0 1.1 0.5 23.1 34.0 0.0 0 52
58 182 8 775 105 122 0.0 0.8 0.5 25.5 57.4 0.0 0 50
59 179 8 747 94 129 0.0 0.7 0.5 34.3 37.3 0.0 0 50
60 176 8 845 96 138 0.0 0.6 0.5 28.3 41.7 0.0 0 52
61 173 8 961 121 110 0.0 0.6 0.5 29.0 52.6 0.0 0 48
62 170 4 911 110 109 0.0 0.9 0.5 33.5 33.3 0.0 0 48
63 167 8 656 109 109 0.0 0.8 0.5 21.9 44.7 0.0 0 52
64 164 8 934 117 105 0.0 0.8 0.5 15.5 50.0 0.0 0 52
65 161 8 972 125 95 0.0 0.8 0.5 24.4 50.0 0.0 0 50
66 158 8 894 125 101 0.0 0.9 0.5 27.2 35.9 0.0 0 52
67 155 8 798 146 129 0.0 1.0 0.5 22.8 58.7 0.0 0 52
68 153 8 901 183 92 0.0 1.1 0.5 23.6 34.5 0.0 0 52
69 150 8 977 197 103 0.0 1.4 0.5 23.6 36.8 0.0 0 52
70 147 8 905 262 93 0.0 1.5 0.5 20.3 63.4 0.0 0 52
71 145 8 995 148 122 0.0 1.9 0.5 20.9 35.3 0.0 0 52
72 142 8 934 230 99 0.0 1.6 0.5 20.0 65.9 0.0 0 52
73 140 8 862 173 100 0.0 1.8 0.5 26.8 46.8 0.0 0 52
74 137 8 924 139 90 0.0 1.7 0.5 16.8 42.5 0.0 0 52
75 135 8 888 168 113 0.0 1.6 0.5 22.9 40.4 0.0 0 52
76 133 8 712 212 84 0.0 1.6 0.5 13.4 46.9 0.0 0 52
77 130 8 868 210 91 0.0 1.7 0.5 17.7 51.2 0.0 0 52
78 128 8 952 307 92 0.0 1.9 0.5 19.7 44.9 0.0 0 50
79 126 8 801 157 107 0.0 2.2 0.5 15.8 39.0 0.0 0 52
80 123 8 849 147 93 0.0 2.1 0.5 15.6 51.4 0.0 0 52
81 121 8 799 154 86 0.0 1.9 0.5 12.2 50.0 0.0 0 52
82 119 8 941 213 82 0.0 1.8 0.5 19.5 41.2 0.0 0 50
83 117 8 751 268 94 0.0 2.0 0.5 20.8 42.6 0.0 0 50
84 115 8 828 198 102 0.0 2.2 0.5 15.5 59.5 0.0 0 52
85 113 8 898 266 123 0.0 2.2 0.5 13.2 85.2 0.0 0 52
86 111 8 943 190 93 0.0 2.4 0.5 19.5 45.1 0.0 0 52
87 109 8 864 183 65 0.0 2.4 0.5 14.9 31.8 0.0 0 52
88 107 8 793 203 93 0.0 2.4 0.5 11.8 35.3 0.0 0 52
89 105 8 752 162 74 1.2 2.4 0.5 13.1 21.4 0.0 0 52
90 103 8 801 149 77 0.0 2.3 0.5 9.7 58.3 0.0 0 52
91 102 8 901 230 99 0.0 2.2 0.5 16.0 25.5 0.0 0 52
92 100 8 826 201 87 0.0 2.4 0.5 12.8 45.7 0.0 0 52
93 98 8 810 196 83 0.0 2.5 0.5 14.0 24.4 0.0 0 52
94 96 8 857 209 68 1.0 2.5 0.5 11.5 27.0 5.1 0 52
95 95 8 771 174 91 0.0 2.6 0.5 10.5 26.5 0.0 0 52
96 93 8 955 210 59 0.0 2.6 0.5 10.0 36.7 0.7 0 52
97 91 8 833 206 53 0.0 2.7 0.5 10.2 19.4 1.4 0 52
98 90 8 888 229 86 0.0 2.8 0.5 8.1 36.0 0.0 0 52
99 88 8 794 186 91 1.0 2.9 0.5 8.3 25.0 0.5 0 52
100 81 8 756 170 72 1.0 2.9 0.5 6.0 23.8 7.0 0 52
101 74 8 791 176 67 0.0 2.9 0.5 4.4 58.3 4.0 0 52
102 67 8 813 213 43 0.0 3.0 0.5 7.0 150.0 4.2 0 52
103 62 8 779 245 39 0.0 3.1 0.5 3.2 16.7 13.0 0 52
104 56 8 767 303 63 0.0 3.2 0.5 4.1 20.0 0.7 0 52
105 52 8 757 270 57 0.0 3.5 0.5 6.4 3.7 0.5 0 52
106 47 8 763 283 41 0.0 3.7 0.5 4.5 0.0 0.0 0 52
107 43 8 768 283 36 0.0 3.7 0.5 2.9 18.2 3.6 0 52
108 39 8 804 283 25 0.0 3.7 0.5 3.1 0.0 6.2 0 52
109 36 8 781 283 24 0.0 3.7 0.5 3.6 6.7 6.7 0 52
110 33 8 738 298 42 0.0 3.7 0.5 3.3 15.4 3.5 0 52
111 30 8 761 298 36 0.0 3.7 0.5 2.2 0.0 4.3 0 52
112 27 8 769 298 37 0.0 3.7 0.5 0.9 0.0 2.2 0 52
113 25 8 745 298 31 0.0 3.7 0.5 1.5 0.0 6.6 0 52
114 23 8 753 298 16 0.0 3.7 0.5 1.3 0.0 2.8 0 52
115 21 8 745 298 11 0.0 3.7 0.5 1.5 0.0 14.0 0 52
116 19 8 747 298 21 0.0 3.7 0.5 2.1 0.0 5.8 0 52
117 13 8 737 298 12 0.0 3.7 0.5 1.0 0.0 10.0 0 52
118 9 8 736 298 4 0.0 3.7 0.5 1.5 0.0 18.5 0 52
119 0 8 739 298 0 0.0 3.7 0.5 1.8 0.0 18.0 0 52
120 0 8 732 298 0 0.0 3.7 0.5 1.2 0.0 21.8 0 52
121 0 8 732 19 -1 0.0 0.0 0.5 0.0 100.0 54.8
Initial Wiring Cost: 645 Final Wiring Cost: 732
############## Percent Wire Cost Reduction: -13
Initial Wire Length: 645 Final Wire Length: 732
************** Percent Wire Length Reduction: -13
Initial Horiz. Wire: 216 Final Horiz. Wire: 147
$$$$$$$$$$$ Percent H-Wire Length Reduction: 32
Initial Vert. Wire: 429 Final Vert. Wire: 585
@@@@@@@@@@@ Percent V-Wire Length Reduction: -36
Before Feeds are Added:
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 82 -20
2 86 -16
LONGEST Block is:2 Its length is:86
BLOCK TOTAL CELL LENGTHS OVER/UNDER TARGET
1 86 -16
2 86 -16
LONGEST Block is:1 Its length is:86
Added: 1 feed-through cells
Removed the cell overlaps --- Will do neighbor interchanges only now
TOTAL INTERCONNECT LENGTH: 994
OVERLAP PENALTY: 0
initialRowControl: 1.650
finalRowControl: 0.300
iter T Wire accept
122 0.001 976 16%
123 0.001 971 0%
124 0.001 971 0%
Total Feed-Alignment Movement (Pass 1): 0
Total Feed-Alignment Movement (Pass 2): 0
Total Feed-Alignment Movement (Pass 3): 0
Total Feed-Alignment Movement (Pass 4): 0
Total Feed-Alignment Movement (Pass 5): 0
Total Feed-Alignment Movement (Pass 6): 0
Total Feed-Alignment Movement (Pass 7): 0
Total Feed-Alignment Movement (Pass 8): 0
The rand generator seed was at globroute() : 987654321
Total Number of Net Segments: 9
Number of Switchable Net Segments: 0
Number of channels: 3
THIS IS THE ORIGINAL NUMBER OF TRACKS: 5
no. of accepted flips: 0
no. of attempted flips: 0
THIS IS THE NUMBER OF TRACKS: 5
FINAL NUMBER OF ROUTING TRACKS: 5
MAX OF CHANNEL: 1 is: 0
MAX OF CHANNEL: 2 is: 4
MAX OF CHANNEL: 3 is: 1
FINAL TOTAL INTERCONNECT LENGTH: 978
FINAL OVERLAP PENALTY: 0 FINAL VALUE OF TOTAL COST IS: 978
MAX NUMBER OF ATTEMPTED FLIPS PER T: 55
cost_scale_factor:3.90616
Number of Feed Thrus: 0
Number of Implicit Feed Thrus: 0
Statistics:
Number of Standard Cells: 10
Number of Pads: 0
Number of Nets: 15
Number of Pins: 46
Usage statistics not available

17
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pin
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$COUNT_1/$AND2_1/$ND2_1$Z 1 $COUNT_1/$AND2_1/$ND2_1 00#Z 17 52 2 1 0
$COUNT_1/$AND2_1/$ND2_1$Z 1 ACOUNT_1 00#A 15 26 2 -1 0
B7 2 $COUNT_1/$FJK3_2 00#K 25 78 3 -1 0
B7 2 $COUNT_1/$FJK3_2 00#J 23 78 3 -1 0
B7 3 $COUNT_1/$AND2_2/$ND2_1 00#A 9 26 2 -1 0
B7 3 ACOUNT_1 01#Z 17 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#K 25 26 2 -1 0
B6 5 $COUNT_1/$FJK3_1 00#J 23 26 2 -1 0
B6 5 $COUNT_1/$AND2_3/$IV_1 01#Z 7 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$FJK3_1 01#Q 81 26 2 -1 0
$COUNT_1/$FJK3_1$Q 6 $COUNT_1/$AND2_1/$ND2_1 00#B 19 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$FJK3_2 00#Q 81 52 2 1 0
$COUNT_1/$FJK3_2$Q 7 $COUNT_1/$AND2_2/$ND2_1 01#B 11 26 2 -1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$ND2_1 00#Z 5 52 2 1 0
$COUNT_1/$AND2_3/$ND2_1$Z 8 $COUNT_1/$AND2_3/$IV_1 00#A 5 26 2 -1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$ND2_1 00#Z 7 52 2 1 0
$COUNT_1/$AND2_4/$ND2_1$Z 9 $COUNT_1/$AND2_4/$IV_1 00#A 3 26 2 -1 0

11
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl1
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$COUNT_1/$AND2_4/$IV_1 0 0 4 26 0 1
$COUNT_1/$AND2_3/$IV_1 4 0 8 26 2 1
$COUNT_1/$AND2_2/$ND2_1 8 0 14 26 0 1
ACOUNT_1 14 0 18 26 2 1
twfeed1 18 0 22 26 0 1
$COUNT_1/$FJK3_1 22 0 86 26 0 1
$COUNT_1/$AND2_3/$ND2_1 0 52 6 78 0 2
$COUNT_1/$AND2_4/$ND2_1 6 52 12 78 2 2
$COUNT_1/$AND2_2/$IV_1 12 52 16 78 2 2
$COUNT_1/$AND2_1/$ND2_1 16 52 22 78 2 2
$COUNT_1/$FJK3_2 22 52 86 78 0 2

2
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.pl2
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@ -1,2 +0,0 @@
1 0 0 86 26 0 0
2 0 52 86 78 0 0

18
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sav
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@ -1,18 +0,0 @@
0.009592
121
0
1
0.000000
0.500000
3.906156
1
1 1 2 37 13
2 2 0 34 65
3 2 2 63 65
4 1 0 59 13
5 1 2 32 13
6 2 0 23 65
7 1 2 12 13
8 2 0 6 65
9 1 0 70 13
10 2 0 70 65

19
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.sv2
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@ -1,19 +0,0 @@
0.001000
123
0
2
0.000000
0.500000
3.906156
1
1 1 2 16 13
2 2 2 19 65
3 2 2 14 65
4 1 0 11 13
5 1 2 6 13
6 2 0 3 65
7 1 0 2 13
8 2 2 9 65
9 1 0 50 13
10 2 0 54 65
11 1 0 84 13

29
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/smred.twf
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net 1
segment channel 2
pin1 1 pin2 7 0 0
net 2
segment channel 3
pin1 41 pin2 42 0 0
segment channel 2
pin1 12 pin2 3 0 0
net 3
segment channel 2
pin1 35 pin2 36 0 0
segment channel 2
pin1 19 pin2 35 0 0
net 4
segment channel 2
pin1 5 pin2 38 0 0
net 5
net 7
segment channel 2
pin1 14 pin2 43 0 0
net 8
segment channel 2
pin1 23 pin2 17 0 0
net 9
net 11
segment channel 2
pin1 25 pin2 31 0 0
net 14
net 15

724
tests/long/se/70.twolf/ref/alpha/tru64/inorder-timing/stats.txt
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---------- Begin Simulation Statistics ----------
sim_seconds 0.041682 # Number of seconds simulated
sim_ticks 41681685000 # Number of ticks simulated
final_tick 41681685000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 117228 # Simulator instruction rate (inst/s)
host_op_rate 117228 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 53167547 # Simulator tick rate (ticks/s)
host_mem_usage 270132 # Number of bytes of host memory used
host_seconds 783.97 # Real time elapsed on the host
sim_insts 91903056 # Number of instructions simulated
sim_ops 91903056 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 178816 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 137216 # Number of bytes read from this memory
system.physmem.bytes_read::total 316032 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 178816 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 178816 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 2794 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 2144 # Number of read requests responded to by this memory
system.physmem.num_reads::total 4938 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 4290038 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 3291997 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 7582035 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 4290038 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 4290038 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 4290038 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 3291997 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 7582035 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 4938 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 4938 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 316032 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 316032 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 443 # Per bank write bursts
system.physmem.perBankRdBursts::1 270 # Per bank write bursts
system.physmem.perBankRdBursts::2 295 # Per bank write bursts
system.physmem.perBankRdBursts::3 499 # Per bank write bursts
system.physmem.perBankRdBursts::4 209 # Per bank write bursts
system.physmem.perBankRdBursts::5 212 # Per bank write bursts
system.physmem.perBankRdBursts::6 207 # Per bank write bursts
system.physmem.perBankRdBursts::7 265 # Per bank write bursts
system.physmem.perBankRdBursts::8 219 # Per bank write bursts
system.physmem.perBankRdBursts::9 249 # Per bank write bursts
system.physmem.perBankRdBursts::10 238 # Per bank write bursts
system.physmem.perBankRdBursts::11 236 # Per bank write bursts
system.physmem.perBankRdBursts::12 379 # Per bank write bursts
system.physmem.perBankRdBursts::13 325 # Per bank write bursts
system.physmem.perBankRdBursts::14 469 # Per bank write bursts
system.physmem.perBankRdBursts::15 423 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 41681611000 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 4938 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 3265 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 1049 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 546 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 74 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 856 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 367.551402 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 223.659981 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 343.121338 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 258 30.14% 30.14% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 183 21.38% 51.52% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 95 11.10% 62.62% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 63 7.36% 69.98% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 46 5.37% 75.35% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 30 3.50% 78.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 51 5.96% 84.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 22 2.57% 87.38% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 108 12.62% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 856 # Bytes accessed per row activation
system.physmem.totQLat 35422000 # Total ticks spent queuing
system.physmem.totMemAccLat 128009500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 24690000 # Total ticks spent in databus transfers
system.physmem.avgQLat 7173.35 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 25923.35 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 7.58 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 7.58 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 0.06 # Data bus utilization in percentage
system.physmem.busUtilRead 0.06 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.03 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 4077 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 82.56 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 8440990.48 # Average gap between requests
system.physmem.pageHitRate 82.56 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 39211333500 # Time in different power states
system.physmem.memoryStateTime::REF 1391780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 1076956500 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 7582035 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 3216 # Transaction distribution
system.membus.trans_dist::ReadResp 3216 # Transaction distribution
system.membus.trans_dist::ReadExReq 1722 # Transaction distribution
system.membus.trans_dist::ReadExResp 1722 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 9876 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 9876 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 316032 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 316032 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 316032 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 5782000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.membus.respLayer1.occupancy 45945000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 0.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 13412628 # Number of BP lookups
system.cpu.branchPred.condPredicted 9650146 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 4269214 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 7424480 # Number of BTB lookups
system.cpu.branchPred.BTBHits 3768498 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 50.757737 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 1029619 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 126 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 19996260 # DTB read hits
system.cpu.dtb.read_misses 10 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 19996270 # DTB read accesses
system.cpu.dtb.write_hits 6501862 # DTB write hits
system.cpu.dtb.write_misses 23 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 6501885 # DTB write accesses
system.cpu.dtb.data_hits 26498122 # DTB hits
system.cpu.dtb.data_misses 33 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 26498155 # DTB accesses
system.cpu.itb.fetch_hits 9956951 # ITB hits
system.cpu.itb.fetch_misses 49 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 9957000 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 389 # Number of system calls
system.cpu.numCycles 83363371 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 5905663 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 7506965 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 73570553 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 62575472 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 136146025 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 2206128 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 5851888 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 8058016 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 38521865 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 26722393 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 3469296 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 799060 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 4268356 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 5972346 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 41.680307 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 57404027 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 458253 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 82970271 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 10393 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 7755613 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 75607758 # Number of cycles cpu stages are processed.
system.cpu.activity 90.696618 # Percentage of cycles cpu is active
system.cpu.comLoads 19996198 # Number of Load instructions committed
system.cpu.comStores 6501103 # Number of Store instructions committed
system.cpu.comBranches 10240685 # Number of Branches instructions committed
system.cpu.comNops 7723346 # Number of Nop instructions committed
system.cpu.comNonSpec 389 # Number of Non-Speculative instructions committed
system.cpu.comInts 43665352 # Number of Integer instructions committed
system.cpu.comFloats 3775974 # Number of Floating Point instructions committed
system.cpu.committedInsts 91903056 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 91903056 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 91903056 # Number of Instructions committed (Total)
system.cpu.cpi 0.907079 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 0.907079 # CPI: Total CPI of All Threads
system.cpu.ipc 1.102439 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 1.102439 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 27683021 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 55680350 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 66.792345 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 34111687 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 49251684 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 59.080725 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 33512024 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 49851347 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 59.800061 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 65336871 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 18026500 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 21.624006 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 29503616 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 53859755 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 64.608418 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 7635 # number of replacements
system.cpu.icache.tags.tagsinuse 1492.194030 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 9945551 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 9520 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1044.700735 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 1492.194030 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.728610 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.728610 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 1885 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 55 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 122 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::2 613 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::3 136 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::4 959 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.920410 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 19923422 # Number of tag accesses
system.cpu.icache.tags.data_accesses 19923422 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 9945551 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 9945551 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 9945551 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 9945551 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 9945551 # number of overall hits
system.cpu.icache.overall_hits::total 9945551 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 11400 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 11400 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 11400 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 11400 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 11400 # number of overall misses
system.cpu.icache.overall_misses::total 11400 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 327908250 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 327908250 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 327908250 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 327908250 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 327908250 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 327908250 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 9956951 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 9956951 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 9956951 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 9956951 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 9956951 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 9956951 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.001145 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.001145 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.001145 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.001145 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.001145 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.001145 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 28763.881579 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 28763.881579 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 28763.881579 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 28763.881579 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 28763.881579 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 7 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 7 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 1880 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 1880 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 1880 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 1880 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 1880 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 1880 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 9520 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 9520 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 9520 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 9520 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 9520 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 268503000 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 268503000 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 268503000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 268503000 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 268503000 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 268503000 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000956 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.000956 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.000956 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 28204.096639 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 28204.096639 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 28204.096639 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 28204.096639 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 18195042 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 9995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 9995 # Transaction distribution
system.cpu.toL2Bus.trans_dist::Writeback 107 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 1748 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 1748 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19040 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 4553 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 23593 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 609280 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 149120 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 758400 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 758400 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 6032000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 14805000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 3522500 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 0.0 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 2189.603987 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 6793 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 3282 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 2.069775 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::writebacks 17.844250 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.inst 1820.772066 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 350.987671 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::writebacks 0.000545 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.055566 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.010711 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.066821 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 3282 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 72 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 129 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::2 700 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::3 168 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::4 2213 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.100159 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 99830 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 99830 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 6726 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::cpu.data 53 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 6779 # number of ReadReq hits
system.cpu.l2cache.Writeback_hits::writebacks 107 # number of Writeback hits
system.cpu.l2cache.Writeback_hits::total 107 # number of Writeback hits
system.cpu.l2cache.ReadExReq_hits::cpu.data 26 # number of ReadExReq hits
system.cpu.l2cache.ReadExReq_hits::total 26 # number of ReadExReq hits
system.cpu.l2cache.demand_hits::cpu.inst 6726 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::cpu.data 79 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 6805 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 6726 # number of overall hits
system.cpu.l2cache.overall_hits::cpu.data 79 # number of overall hits
system.cpu.l2cache.overall_hits::total 6805 # number of overall hits
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system.cpu.l2cache.ReadReq_misses::total 3216 # number of ReadReq misses
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system.cpu.l2cache.overall_miss_latency::total 344350500 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 9520 # number of ReadReq accesses(hits+misses)
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system.cpu.l2cache.ReadReq_accesses::total 9995 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::writebacks 107 # number of Writeback accesses(hits+misses)
system.cpu.l2cache.Writeback_accesses::total 107 # number of Writeback accesses(hits+misses)
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system.cpu.l2cache.overall_accesses::total 11743 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.293487 # miss rate for ReadReq accesses
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system.cpu.l2cache.overall_miss_rate::cpu.inst 0.293487 # miss rate for overall accesses
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system.cpu.l2cache.overall_miss_rate::total 0.420506 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68520.221904 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 74034.952607 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 69243.858831 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70651.713124 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70651.713124 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 69734.811665 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68520.221904 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 71317.630597 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 69734.811665 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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system.cpu.l2cache.demand_mshr_misses::cpu.inst 2794 # number of demand (read+write) MSHR misses
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system.cpu.l2cache.overall_mshr_misses::cpu.inst 2794 # number of overall MSHR misses
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system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 25982750 # number of ReadReq MSHR miss cycles
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system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 126562000 # number of demand (read+write) MSHR miss cycles
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system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.888421 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.321761 # mshr miss rate for ReadReq accesses
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system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.985126 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for demand accesses
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system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.293487 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.964462 # mshr miss rate for overall accesses
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system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 61570.497630 # average ReadReq mshr miss latency
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system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58408.391405 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58408.391405 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 55947.208304 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 59030.783582 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 57286.046983 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 157 # number of replacements
system.cpu.dcache.tags.tagsinuse 1441.383569 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 26488452 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 2223 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 11915.632928 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 1441.383569 # Average occupied blocks per requestor
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system.cpu.dcache.tags.occ_task_id_blocks::1024 2066 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 57 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::2 212 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::3 403 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::4 1372 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.504395 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 52996825 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 52996825 # Number of data accesses
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system.cpu.dcache.overall_misses::total 8849 # number of overall misses
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system.cpu.dcache.overall_accesses::total 26497301 # number of overall (read+write) accesses
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system.cpu.dcache.ReadReq_miss_rate::total 0.000029 # miss rate for ReadReq accesses
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system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68917.098446 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 68917.098446 # average ReadReq miss latency
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system.cpu.dcache.overall_avg_miss_latency::cpu.data 60227.822353 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 60227.822353 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 24052 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 836 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 28.770335 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.writebacks::writebacks 107 # number of writebacks
system.cpu.dcache.writebacks::total 107 # number of writebacks
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 104 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 104 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 6522 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 6522 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 6626 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 6626 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 6626 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 6626 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 475 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 475 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 1748 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 1748 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 2223 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 2223 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 2223 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 32266250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 32266250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 123679750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 123679750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 155946000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 155946000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 155946000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 155946000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.000024 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000269 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.000084 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.000084 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 67928.947368 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 67928.947368 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 70755.005721 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 70755.005721 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 70151.147099 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 70151.147099 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------

346
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/config.ini
View file

@ -1,346 +0,0 @@
[root]
type=Root
children=system
eventq_index=0
full_system=false
sim_quantum=0
time_sync_enable=false
time_sync_period=100000000000
time_sync_spin_threshold=100000000
[system]
type=System
children=clk_domain cpu cpu_clk_domain dvfs_handler membus physmem voltage_domain
boot_osflags=a
cache_line_size=64
clk_domain=system.clk_domain
eventq_index=0
init_param=0
kernel=
kernel_addr_check=true
load_addr_mask=1099511627775
load_offset=0
mem_mode=timing
mem_ranges=
memories=system.physmem
num_work_ids=16
readfile=
symbolfile=
work_begin_ckpt_count=0
work_begin_cpu_id_exit=-1
work_begin_exit_count=0
work_cpus_ckpt_count=0
work_end_ckpt_count=0
work_end_exit_count=0
work_item_id=-1
system_port=system.membus.slave[0]
[system.clk_domain]
type=SrcClockDomain
clock=1000
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.cpu]
type=InOrderCPU
children=branchPred dcache dtb icache interrupts isa itb l2cache toL2Bus tracer workload
activity=0
branchPred=system.cpu.branchPred
cachePorts=2
checker=Null
clk_domain=system.cpu_clk_domain
cpu_id=0
div16Latency=1
div16RepeatRate=1
div24Latency=1
div24RepeatRate=1
div32Latency=1
div32RepeatRate=1
div8Latency=1
div8RepeatRate=1
do_checkpoint_insts=true
do_quiesce=true
do_statistics_insts=true
dtb=system.cpu.dtb
eventq_index=0
fetchBuffSize=4
function_trace=false
function_trace_start=0
interrupts=system.cpu.interrupts
isa=system.cpu.isa
itb=system.cpu.itb
max_insts_all_threads=0
max_insts_any_thread=0
max_loads_all_threads=0
max_loads_any_thread=0
memBlockSize=64
multLatency=1
multRepeatRate=1
numThreads=1
profile=0
progress_interval=0
simpoint_start_insts=
socket_id=0
stageTracing=false
stageWidth=4
switched_out=false
system=system
threadModel=SMT
tracer=system.cpu.tracer
workload=system.cpu.workload
dcache_port=system.cpu.dcache.cpu_side
icache_port=system.cpu.icache.cpu_side
[system.cpu.branchPred]
type=BranchPredictor
BTBEntries=4096
BTBTagSize=16
RASSize=16
choiceCtrBits=2
choicePredictorSize=8192
eventq_index=0
globalCtrBits=2
globalPredictorSize=8192
instShiftAmt=2
localCtrBits=2
localHistoryTableSize=2048
localPredictorSize=2048
numThreads=1
predType=tournament
[system.cpu.dcache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=262144
system=system
tags=system.cpu.dcache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.dcache_port
mem_side=system.cpu.toL2Bus.slave[1]
[system.cpu.dcache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=262144
[system.cpu.dtb]
type=AlphaTLB
eventq_index=0
size=64
[system.cpu.icache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=2
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=2
is_top_level=true
max_miss_count=0
mshrs=4
prefetch_on_access=false
prefetcher=Null
response_latency=2
sequential_access=false
size=131072
system=system
tags=system.cpu.icache.tags
tgts_per_mshr=20
two_queue=false
write_buffers=8
cpu_side=system.cpu.icache_port
mem_side=system.cpu.toL2Bus.slave[0]
[system.cpu.icache.tags]
type=LRU
assoc=2
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=2
sequential_access=false
size=131072
[system.cpu.interrupts]
type=AlphaInterrupts
eventq_index=0
[system.cpu.isa]
type=AlphaISA
eventq_index=0
system=system
[system.cpu.itb]
type=AlphaTLB
eventq_index=0
size=48
[system.cpu.l2cache]
type=BaseCache
children=tags
addr_ranges=0:18446744073709551615
assoc=8
clk_domain=system.cpu_clk_domain
eventq_index=0
forward_snoops=true
hit_latency=20
is_top_level=false
max_miss_count=0
mshrs=20
prefetch_on_access=false
prefetcher=Null
response_latency=20
sequential_access=false
size=2097152
system=system
tags=system.cpu.l2cache.tags
tgts_per_mshr=12
two_queue=false
write_buffers=8
cpu_side=system.cpu.toL2Bus.master[0]
mem_side=system.membus.slave[1]
[system.cpu.l2cache.tags]
type=LRU
assoc=8
block_size=64
clk_domain=system.cpu_clk_domain
eventq_index=0
hit_latency=20
sequential_access=false
size=2097152
[system.cpu.toL2Bus]
type=CoherentBus
clk_domain=system.cpu_clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=32
master=system.cpu.l2cache.cpu_side
slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
[system.cpu.tracer]
type=ExeTracer
eventq_index=0
[system.cpu.workload]
type=LiveProcess
cmd=hello
cwd=
egid=100
env=
errout=cerr
euid=100
eventq_index=0
executable=/scratch/nilay/GEM5/gem5/tests/test-progs/hello/bin/alpha/linux/hello
gid=100
input=cin
max_stack_size=67108864
output=cout
pid=100
ppid=99
simpoint=0
system=system
uid=100
[system.cpu_clk_domain]
type=SrcClockDomain
clock=500
domain_id=-1
eventq_index=0
init_perf_level=0
voltage_domain=system.voltage_domain
[system.dvfs_handler]
type=DVFSHandler
domains=
enable=false
eventq_index=0
sys_clk_domain=system.clk_domain
transition_latency=100000000
[system.membus]
type=CoherentBus
clk_domain=system.clk_domain
eventq_index=0
header_cycles=1
system=system
use_default_range=false
width=8
master=system.physmem.port
slave=system.system_port system.cpu.l2cache.mem_side
[system.physmem]
type=DRAMCtrl
activation_limit=4
addr_mapping=RoRaBaChCo
banks_per_rank=8
burst_length=8
channels=1
clk_domain=system.clk_domain
conf_table_reported=true
device_bus_width=8
device_rowbuffer_size=1024
devices_per_rank=8
eventq_index=0
in_addr_map=true
max_accesses_per_row=16
mem_sched_policy=frfcfs
min_writes_per_switch=16
null=false
page_policy=open_adaptive
range=0:134217727
ranks_per_channel=2
read_buffer_size=32
static_backend_latency=10000
static_frontend_latency=10000
tBURST=5000
tCK=1250
tCL=13750
tRAS=35000
tRCD=13750
tREFI=7800000
tRFC=260000
tRP=13750
tRRD=6000
tRTP=7500
tRTW=2500
tWR=15000
tWTR=7500
tXAW=30000
write_buffer_size=64
write_high_thresh_perc=85
write_low_thresh_perc=50
port=system.membus.master[0]
[system.voltage_domain]
type=VoltageDomain
eventq_index=0
voltage=1.000000

1
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simerr
View file

@ -1 +0,0 @@
warn: Sockets disabled, not accepting gdb connections

12
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/simout
View file

@ -1,12 +0,0 @@
gem5 Simulator System. http://gem5.org
gem5 is copyrighted software; use the --copyright option for details.
gem5 compiled Jan 22 2014 16:27:55
gem5 started Jan 22 2014 17:24:08
gem5 executing on u200540-lin
command line: build/ALPHA/gem5.opt -d build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing -re tests/run.py build/ALPHA/tests/opt/quick/se/00.hello/alpha/linux/inorder-timing
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
info: Increasing stack size by one page.
Hello world!
Exiting @ tick 25485000 because target called exit()

701
tests/quick/se/00.hello/ref/alpha/linux/inorder-timing/stats.txt
View file

@ -1,701 +0,0 @@
---------- Begin Simulation Statistics ----------
sim_seconds 0.000026 # Number of seconds simulated
sim_ticks 25552000 # Number of ticks simulated
final_tick 25552000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
sim_freq 1000000000000 # Frequency of simulated ticks
host_inst_rate 78387 # Simulator instruction rate (inst/s)
host_op_rate 78372 # Simulator op (including micro ops) rate (op/s)
host_tick_rate 313333088 # Simulator tick rate (ticks/s)
host_mem_usage 263656 # Number of bytes of host memory used
host_seconds 0.08 # Real time elapsed on the host
sim_insts 6390 # Number of instructions simulated
sim_ops 6390 # Number of ops (including micro ops) simulated
system.voltage_domain.voltage 1 # Voltage in Volts
system.clk_domain.clock 1000 # Clock period in ticks
system.physmem.bytes_read::cpu.inst 19200 # Number of bytes read from this memory
system.physmem.bytes_read::cpu.data 10752 # Number of bytes read from this memory
system.physmem.bytes_read::total 29952 # Number of bytes read from this memory
system.physmem.bytes_inst_read::cpu.inst 19200 # Number of instructions bytes read from this memory
system.physmem.bytes_inst_read::total 19200 # Number of instructions bytes read from this memory
system.physmem.num_reads::cpu.inst 300 # Number of read requests responded to by this memory
system.physmem.num_reads::cpu.data 168 # Number of read requests responded to by this memory
system.physmem.num_reads::total 468 # Number of read requests responded to by this memory
system.physmem.bw_read::cpu.inst 751408892 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::cpu.data 420788979 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_read::total 1172197871 # Total read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::cpu.inst 751408892 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_inst_read::total 751408892 # Instruction read bandwidth from this memory (bytes/s)
system.physmem.bw_total::cpu.inst 751408892 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::cpu.data 420788979 # Total bandwidth to/from this memory (bytes/s)
system.physmem.bw_total::total 1172197871 # Total bandwidth to/from this memory (bytes/s)
system.physmem.readReqs 469 # Number of read requests accepted
system.physmem.writeReqs 0 # Number of write requests accepted
system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
system.physmem.perBankRdBursts::0 65 # Per bank write bursts
system.physmem.perBankRdBursts::1 29 # Per bank write bursts
system.physmem.perBankRdBursts::2 27 # Per bank write bursts
system.physmem.perBankRdBursts::3 47 # Per bank write bursts
system.physmem.perBankRdBursts::4 41 # Per bank write bursts
system.physmem.perBankRdBursts::5 19 # Per bank write bursts
system.physmem.perBankRdBursts::6 1 # Per bank write bursts
system.physmem.perBankRdBursts::7 3 # Per bank write bursts
system.physmem.perBankRdBursts::8 0 # Per bank write bursts
system.physmem.perBankRdBursts::9 1 # Per bank write bursts
system.physmem.perBankRdBursts::10 19 # Per bank write bursts
system.physmem.perBankRdBursts::11 25 # Per bank write bursts
system.physmem.perBankRdBursts::12 15 # Per bank write bursts
system.physmem.perBankRdBursts::13 119 # Per bank write bursts
system.physmem.perBankRdBursts::14 46 # Per bank write bursts
system.physmem.perBankRdBursts::15 12 # Per bank write bursts
system.physmem.perBankWrBursts::0 0 # Per bank write bursts
system.physmem.perBankWrBursts::1 0 # Per bank write bursts
system.physmem.perBankWrBursts::2 0 # Per bank write bursts
system.physmem.perBankWrBursts::3 0 # Per bank write bursts
system.physmem.perBankWrBursts::4 0 # Per bank write bursts
system.physmem.perBankWrBursts::5 0 # Per bank write bursts
system.physmem.perBankWrBursts::6 0 # Per bank write bursts
system.physmem.perBankWrBursts::7 0 # Per bank write bursts
system.physmem.perBankWrBursts::8 0 # Per bank write bursts
system.physmem.perBankWrBursts::9 0 # Per bank write bursts
system.physmem.perBankWrBursts::10 0 # Per bank write bursts
system.physmem.perBankWrBursts::11 0 # Per bank write bursts
system.physmem.perBankWrBursts::12 0 # Per bank write bursts
system.physmem.perBankWrBursts::13 0 # Per bank write bursts
system.physmem.perBankWrBursts::14 0 # Per bank write bursts
system.physmem.perBankWrBursts::15 0 # Per bank write bursts
system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
system.physmem.totGap 25537500 # Total gap between requests
system.physmem.readPktSize::0 0 # Read request sizes (log2)
system.physmem.readPktSize::1 0 # Read request sizes (log2)
system.physmem.readPktSize::2 0 # Read request sizes (log2)
system.physmem.readPktSize::3 0 # Read request sizes (log2)
system.physmem.readPktSize::4 0 # Read request sizes (log2)
system.physmem.readPktSize::5 0 # Read request sizes (log2)
system.physmem.readPktSize::6 469 # Read request sizes (log2)
system.physmem.writePktSize::0 0 # Write request sizes (log2)
system.physmem.writePktSize::1 0 # Write request sizes (log2)
system.physmem.writePktSize::2 0 # Write request sizes (log2)
system.physmem.writePktSize::3 0 # Write request sizes (log2)
system.physmem.writePktSize::4 0 # Write request sizes (log2)
system.physmem.writePktSize::5 0 # Write request sizes (log2)
system.physmem.writePktSize::6 0 # Write request sizes (log2)
system.physmem.rdQLenPdf::0 313 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::1 127 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::2 21 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::3 8 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
system.physmem.bytesPerActivate::samples 86 # Bytes accessed per row activation
system.physmem.bytesPerActivate::mean 330.418605 # Bytes accessed per row activation
system.physmem.bytesPerActivate::gmean 204.922237 # Bytes accessed per row activation
system.physmem.bytesPerActivate::stdev 319.300576 # Bytes accessed per row activation
system.physmem.bytesPerActivate::0-127 27 31.40% 31.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::128-255 21 24.42% 55.81% # Bytes accessed per row activation
system.physmem.bytesPerActivate::256-383 10 11.63% 67.44% # Bytes accessed per row activation
system.physmem.bytesPerActivate::384-511 8 9.30% 76.74% # Bytes accessed per row activation
system.physmem.bytesPerActivate::512-639 1 1.16% 77.91% # Bytes accessed per row activation
system.physmem.bytesPerActivate::640-767 3 3.49% 81.40% # Bytes accessed per row activation
system.physmem.bytesPerActivate::768-895 7 8.14% 89.53% # Bytes accessed per row activation
system.physmem.bytesPerActivate::896-1023 2 2.33% 91.86% # Bytes accessed per row activation
system.physmem.bytesPerActivate::1024-1151 7 8.14% 100.00% # Bytes accessed per row activation
system.physmem.bytesPerActivate::total 86 # Bytes accessed per row activation
system.physmem.totQLat 3845750 # Total ticks spent queuing
system.physmem.totMemAccLat 12639500 # Total ticks spent from burst creation until serviced by the DRAM
system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
system.physmem.avgQLat 8199.89 # Average queueing delay per DRAM burst
system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
system.physmem.avgMemAccLat 26949.89 # Average memory access latency per DRAM burst
system.physmem.avgRdBW 1174.70 # Average DRAM read bandwidth in MiByte/s
system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
system.physmem.avgRdBWSys 1174.70 # Average system read bandwidth in MiByte/s
system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
system.physmem.busUtil 9.18 # Data bus utilization in percentage
system.physmem.busUtilRead 9.18 # Data bus utilization in percentage for reads
system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
system.physmem.avgRdQLen 1.50 # Average read queue length when enqueuing
system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
system.physmem.readRowHits 378 # Number of row buffer hits during reads
system.physmem.writeRowHits 0 # Number of row buffer hits during writes
system.physmem.readRowHitRate 80.60 # Row buffer hit rate for reads
system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
system.physmem.avgGap 54450.96 # Average gap between requests
system.physmem.pageHitRate 80.60 # Row buffer hit rate, read and write combined
system.physmem.memoryStateTime::IDLE 13500 # Time in different power states
system.physmem.memoryStateTime::REF 780000 # Time in different power states
system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
system.physmem.memoryStateTime::ACT 22839000 # Time in different power states
system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
system.membus.throughput 1172197871 # Throughput (bytes/s)
system.membus.trans_dist::ReadReq 396 # Transaction distribution
system.membus.trans_dist::ReadResp 395 # Transaction distribution
system.membus.trans_dist::ReadExReq 73 # Transaction distribution
system.membus.trans_dist::ReadExResp 73 # Transaction distribution
system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 937 # Packet count per connected master and slave (bytes)
system.membus.pkt_count::total 937 # Packet count per connected master and slave (bytes)
system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.tot_pkt_size::total 29952 # Cumulative packet size per connected master and slave (bytes)
system.membus.data_through_bus 29952 # Total data (bytes)
system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.membus.reqLayer0.occupancy 560000 # Layer occupancy (ticks)
system.membus.reqLayer0.utilization 2.2 # Layer utilization (%)
system.membus.respLayer1.occupancy 4371000 # Layer occupancy (ticks)
system.membus.respLayer1.utilization 17.1 # Layer utilization (%)
system.cpu_clk_domain.clock 500 # Clock period in ticks
system.cpu.branchPred.lookups 1632 # Number of BP lookups
system.cpu.branchPred.condPredicted 1160 # Number of conditional branches predicted
system.cpu.branchPred.condIncorrect 706 # Number of conditional branches incorrect
system.cpu.branchPred.BTBLookups 1266 # Number of BTB lookups
system.cpu.branchPred.BTBHits 352 # Number of BTB hits
system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
system.cpu.branchPred.BTBHitPct 27.804107 # BTB Hit Percentage
system.cpu.branchPred.usedRAS 126 # Number of times the RAS was used to get a target.
system.cpu.branchPred.RASInCorrect 0 # Number of incorrect RAS predictions.
system.cpu.dtb.fetch_hits 0 # ITB hits
system.cpu.dtb.fetch_misses 0 # ITB misses
system.cpu.dtb.fetch_acv 0 # ITB acv
system.cpu.dtb.fetch_accesses 0 # ITB accesses
system.cpu.dtb.read_hits 1183 # DTB read hits
system.cpu.dtb.read_misses 7 # DTB read misses
system.cpu.dtb.read_acv 0 # DTB read access violations
system.cpu.dtb.read_accesses 1190 # DTB read accesses
system.cpu.dtb.write_hits 890 # DTB write hits
system.cpu.dtb.write_misses 3 # DTB write misses
system.cpu.dtb.write_acv 0 # DTB write access violations
system.cpu.dtb.write_accesses 893 # DTB write accesses
system.cpu.dtb.data_hits 2073 # DTB hits
system.cpu.dtb.data_misses 10 # DTB misses
system.cpu.dtb.data_acv 0 # DTB access violations
system.cpu.dtb.data_accesses 2083 # DTB accesses
system.cpu.itb.fetch_hits 915 # ITB hits
system.cpu.itb.fetch_misses 17 # ITB misses
system.cpu.itb.fetch_acv 0 # ITB acv
system.cpu.itb.fetch_accesses 932 # ITB accesses
system.cpu.itb.read_hits 0 # DTB read hits
system.cpu.itb.read_misses 0 # DTB read misses
system.cpu.itb.read_acv 0 # DTB read access violations
system.cpu.itb.read_accesses 0 # DTB read accesses
system.cpu.itb.write_hits 0 # DTB write hits
system.cpu.itb.write_misses 0 # DTB write misses
system.cpu.itb.write_acv 0 # DTB write access violations
system.cpu.itb.write_accesses 0 # DTB write accesses
system.cpu.itb.data_hits 0 # DTB hits
system.cpu.itb.data_misses 0 # DTB misses
system.cpu.itb.data_acv 0 # DTB access violations
system.cpu.itb.data_accesses 0 # DTB accesses
system.cpu.workload.num_syscalls 17 # Number of system calls
system.cpu.numCycles 51105 # number of cpu cycles simulated
system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
system.cpu.branch_predictor.predictedTaken 502 # Number of Branches Predicted As Taken (True).
system.cpu.branch_predictor.predictedNotTaken 1130 # Number of Branches Predicted As Not Taken (False).
system.cpu.regfile_manager.intRegFileReads 5177 # Number of Reads from Int. Register File
system.cpu.regfile_manager.intRegFileWrites 4567 # Number of Writes to Int. Register File
system.cpu.regfile_manager.intRegFileAccesses 9744 # Total Accesses (Read+Write) to the Int. Register File
system.cpu.regfile_manager.floatRegFileReads 8 # Number of Reads from FP Register File
system.cpu.regfile_manager.floatRegFileWrites 2 # Number of Writes to FP Register File
system.cpu.regfile_manager.floatRegFileAccesses 10 # Total Accesses (Read+Write) to the FP Register File
system.cpu.regfile_manager.regForwards 2973 # Number of Registers Read Through Forwarding Logic
system.cpu.agen_unit.agens 2152 # Number of Address Generations
system.cpu.execution_unit.predictedTakenIncorrect 320 # Number of Branches Incorrectly Predicted As Taken.
system.cpu.execution_unit.predictedNotTakenIncorrect 325 # Number of Branches Incorrectly Predicted As Not Taken).
system.cpu.execution_unit.mispredicted 645 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.predicted 406 # Number of Branches Incorrectly Predicted
system.cpu.execution_unit.mispredictPct 61.370124 # Percentage of Incorrect Branches Predicts
system.cpu.execution_unit.executions 4448 # Number of Instructions Executed.
system.cpu.mult_div_unit.multiplies 1 # Number of Multipy Operations Executed
system.cpu.mult_div_unit.divides 0 # Number of Divide Operations Executed
system.cpu.contextSwitches 1 # Number of context switches
system.cpu.threadCycles 11594 # Total Number of Cycles A Thread Was Active in CPU (Per-Thread)
system.cpu.smtCycles 0 # Total number of cycles that the CPU was in SMT-mode
system.cpu.timesIdled 467 # Number of times that the entire CPU went into an idle state and unscheduled itself
system.cpu.idleCycles 43730 # Number of cycles cpu's stages were not processed
system.cpu.runCycles 7375 # Number of cycles cpu stages are processed.
system.cpu.activity 14.431073 # Percentage of cycles cpu is active
system.cpu.comLoads 1183 # Number of Load instructions committed
system.cpu.comStores 865 # Number of Store instructions committed
system.cpu.comBranches 1050 # Number of Branches instructions committed
system.cpu.comNops 17 # Number of Nop instructions committed
system.cpu.comNonSpec 17 # Number of Non-Speculative instructions committed
system.cpu.comInts 3254 # Number of Integer instructions committed
system.cpu.comFloats 2 # Number of Floating Point instructions committed
system.cpu.committedInsts 6390 # Number of Instructions committed (Per-Thread)
system.cpu.committedOps 6390 # Number of Ops committed (Per-Thread)
system.cpu.smtCommittedInsts 0 # Number of SMT Instructions committed (Per-Thread)
system.cpu.committedInsts_total 6390 # Number of Instructions committed (Total)
system.cpu.cpi 7.997653 # CPI: Cycles Per Instruction (Per-Thread)
system.cpu.smt_cpi nan # CPI: Total SMT-CPI
system.cpu.cpi_total 7.997653 # CPI: Total CPI of All Threads
system.cpu.ipc 0.125037 # IPC: Instructions Per Cycle (Per-Thread)
system.cpu.smt_ipc nan # IPC: Total SMT-IPC
system.cpu.ipc_total 0.125037 # IPC: Total IPC of All Threads
system.cpu.stage0.idleCycles 46181 # Number of cycles 0 instructions are processed.
system.cpu.stage0.runCycles 4924 # Number of cycles 1+ instructions are processed.
system.cpu.stage0.utilization 9.635065 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage1.idleCycles 47212 # Number of cycles 0 instructions are processed.
system.cpu.stage1.runCycles 3893 # Number of cycles 1+ instructions are processed.
system.cpu.stage1.utilization 7.617650 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage2.idleCycles 46944 # Number of cycles 0 instructions are processed.
system.cpu.stage2.runCycles 4161 # Number of cycles 1+ instructions are processed.
system.cpu.stage2.utilization 8.142060 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage3.idleCycles 49775 # Number of cycles 0 instructions are processed.
system.cpu.stage3.runCycles 1330 # Number of cycles 1+ instructions are processed.
system.cpu.stage3.utilization 2.602485 # Percentage of cycles stage was utilized (processing insts).
system.cpu.stage4.idleCycles 46641 # Number of cycles 0 instructions are processed.
system.cpu.stage4.runCycles 4464 # Number of cycles 1+ instructions are processed.
system.cpu.stage4.utilization 8.734957 # Percentage of cycles stage was utilized (processing insts).
system.cpu.icache.tags.replacements 0 # number of replacements
system.cpu.icache.tags.tagsinuse 142.073249 # Cycle average of tags in use
system.cpu.icache.tags.total_refs 560 # Total number of references to valid blocks.
system.cpu.icache.tags.sampled_refs 301 # Sample count of references to valid blocks.
system.cpu.icache.tags.avg_refs 1.860465 # Average number of references to valid blocks.
system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.icache.tags.occ_blocks::cpu.inst 142.073249 # Average occupied blocks per requestor
system.cpu.icache.tags.occ_percent::cpu.inst 0.069372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_percent::total 0.069372 # Average percentage of cache occupancy
system.cpu.icache.tags.occ_task_id_blocks::1024 301 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id
system.cpu.icache.tags.age_task_id_blocks_1024::1 175 # Occupied blocks per task id
system.cpu.icache.tags.occ_task_id_percent::1024 0.146973 # Percentage of cache occupancy per task id
system.cpu.icache.tags.tag_accesses 2131 # Number of tag accesses
system.cpu.icache.tags.data_accesses 2131 # Number of data accesses
system.cpu.icache.ReadReq_hits::cpu.inst 560 # number of ReadReq hits
system.cpu.icache.ReadReq_hits::total 560 # number of ReadReq hits
system.cpu.icache.demand_hits::cpu.inst 560 # number of demand (read+write) hits
system.cpu.icache.demand_hits::total 560 # number of demand (read+write) hits
system.cpu.icache.overall_hits::cpu.inst 560 # number of overall hits
system.cpu.icache.overall_hits::total 560 # number of overall hits
system.cpu.icache.ReadReq_misses::cpu.inst 355 # number of ReadReq misses
system.cpu.icache.ReadReq_misses::total 355 # number of ReadReq misses
system.cpu.icache.demand_misses::cpu.inst 355 # number of demand (read+write) misses
system.cpu.icache.demand_misses::total 355 # number of demand (read+write) misses
system.cpu.icache.overall_misses::cpu.inst 355 # number of overall misses
system.cpu.icache.overall_misses::total 355 # number of overall misses
system.cpu.icache.ReadReq_miss_latency::cpu.inst 24875750 # number of ReadReq miss cycles
system.cpu.icache.ReadReq_miss_latency::total 24875750 # number of ReadReq miss cycles
system.cpu.icache.demand_miss_latency::cpu.inst 24875750 # number of demand (read+write) miss cycles
system.cpu.icache.demand_miss_latency::total 24875750 # number of demand (read+write) miss cycles
system.cpu.icache.overall_miss_latency::cpu.inst 24875750 # number of overall miss cycles
system.cpu.icache.overall_miss_latency::total 24875750 # number of overall miss cycles
system.cpu.icache.ReadReq_accesses::cpu.inst 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.ReadReq_accesses::total 915 # number of ReadReq accesses(hits+misses)
system.cpu.icache.demand_accesses::cpu.inst 915 # number of demand (read+write) accesses
system.cpu.icache.demand_accesses::total 915 # number of demand (read+write) accesses
system.cpu.icache.overall_accesses::cpu.inst 915 # number of overall (read+write) accesses
system.cpu.icache.overall_accesses::total 915 # number of overall (read+write) accesses
system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.387978 # miss rate for ReadReq accesses
system.cpu.icache.ReadReq_miss_rate::total 0.387978 # miss rate for ReadReq accesses
system.cpu.icache.demand_miss_rate::cpu.inst 0.387978 # miss rate for demand accesses
system.cpu.icache.demand_miss_rate::total 0.387978 # miss rate for demand accesses
system.cpu.icache.overall_miss_rate::cpu.inst 0.387978 # miss rate for overall accesses
system.cpu.icache.overall_miss_rate::total 0.387978 # miss rate for overall accesses
system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 70072.535211 # average ReadReq miss latency
system.cpu.icache.ReadReq_avg_miss_latency::total 70072.535211 # average ReadReq miss latency
system.cpu.icache.demand_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
system.cpu.icache.demand_avg_miss_latency::total 70072.535211 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::cpu.inst 70072.535211 # average overall miss latency
system.cpu.icache.overall_avg_miss_latency::total 70072.535211 # average overall miss latency
system.cpu.icache.blocked_cycles::no_mshrs 89 # number of cycles access was blocked
system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.icache.avg_blocked_cycles::no_mshrs 89 # average number of cycles each access was blocked
system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.icache.fast_writes 0 # number of fast writes performed
system.cpu.icache.cache_copies 0 # number of cache copies performed
system.cpu.icache.ReadReq_mshr_hits::cpu.inst 53 # number of ReadReq MSHR hits
system.cpu.icache.ReadReq_mshr_hits::total 53 # number of ReadReq MSHR hits
system.cpu.icache.demand_mshr_hits::cpu.inst 53 # number of demand (read+write) MSHR hits
system.cpu.icache.demand_mshr_hits::total 53 # number of demand (read+write) MSHR hits
system.cpu.icache.overall_mshr_hits::cpu.inst 53 # number of overall MSHR hits
system.cpu.icache.overall_mshr_hits::total 53 # number of overall MSHR hits
system.cpu.icache.ReadReq_mshr_misses::cpu.inst 302 # number of ReadReq MSHR misses
system.cpu.icache.ReadReq_mshr_misses::total 302 # number of ReadReq MSHR misses
system.cpu.icache.demand_mshr_misses::cpu.inst 302 # number of demand (read+write) MSHR misses
system.cpu.icache.demand_mshr_misses::total 302 # number of demand (read+write) MSHR misses
system.cpu.icache.overall_mshr_misses::cpu.inst 302 # number of overall MSHR misses
system.cpu.icache.overall_mshr_misses::total 302 # number of overall MSHR misses
system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 21058500 # number of ReadReq MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_latency::total 21058500 # number of ReadReq MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::cpu.inst 21058500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.demand_mshr_miss_latency::total 21058500 # number of demand (read+write) MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::cpu.inst 21058500 # number of overall MSHR miss cycles
system.cpu.icache.overall_mshr_miss_latency::total 21058500 # number of overall MSHR miss cycles
system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.ReadReq_mshr_miss_rate::total 0.330055 # mshr miss rate for ReadReq accesses
system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.demand_mshr_miss_rate::total 0.330055 # mshr miss rate for demand accesses
system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.overall_mshr_miss_rate::total 0.330055 # mshr miss rate for overall accesses
system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 69730.132450 # average ReadReq mshr miss latency
system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 69730.132450 # average ReadReq mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
system.cpu.icache.demand_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 69730.132450 # average overall mshr miss latency
system.cpu.icache.overall_avg_mshr_miss_latency::total 69730.132450 # average overall mshr miss latency
system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.toL2Bus.throughput 1174702567 # Throughput (bytes/s)
system.cpu.toL2Bus.trans_dist::ReadReq 397 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadResp 396 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExReq 73 # Transaction distribution
system.cpu.toL2Bus.trans_dist::ReadExResp 73 # Transaction distribution
system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 336 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.pkt_count::total 939 # Packet count per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19264 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 10752 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.tot_pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
system.cpu.toL2Bus.data_through_bus 30016 # Total data (bytes)
system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
system.cpu.toL2Bus.reqLayer0.occupancy 235000 # Layer occupancy (ticks)
system.cpu.toL2Bus.reqLayer0.utilization 0.9 # Layer utilization (%)
system.cpu.toL2Bus.respLayer0.occupancy 508000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
system.cpu.toL2Bus.respLayer1.occupancy 276000 # Layer occupancy (ticks)
system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%)
system.cpu.l2cache.tags.replacements 0 # number of replacements
system.cpu.l2cache.tags.tagsinuse 198.803908 # Cycle average of tags in use
system.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks.
system.cpu.l2cache.tags.sampled_refs 395 # Sample count of references to valid blocks.
system.cpu.l2cache.tags.avg_refs 0.002532 # Average number of references to valid blocks.
system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.l2cache.tags.occ_blocks::cpu.inst 142.109548 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_blocks::cpu.data 56.694360 # Average occupied blocks per requestor
system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004337 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::cpu.data 0.001730 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_percent::total 0.006067 # Average percentage of cache occupancy
system.cpu.l2cache.tags.occ_task_id_blocks::1024 395 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::0 155 # Occupied blocks per task id
system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id
system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012054 # Percentage of cache occupancy per task id
system.cpu.l2cache.tags.tag_accesses 4228 # Number of tag accesses
system.cpu.l2cache.tags.data_accesses 4228 # Number of data accesses
system.cpu.l2cache.ReadReq_hits::cpu.inst 1 # number of ReadReq hits
system.cpu.l2cache.ReadReq_hits::total 1 # number of ReadReq hits
system.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits
system.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits
system.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits
system.cpu.l2cache.overall_hits::total 1 # number of overall hits
system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::cpu.data 95 # number of ReadReq misses
system.cpu.l2cache.ReadReq_misses::total 396 # number of ReadReq misses
system.cpu.l2cache.ReadExReq_misses::cpu.data 73 # number of ReadExReq misses
system.cpu.l2cache.ReadExReq_misses::total 73 # number of ReadExReq misses
system.cpu.l2cache.demand_misses::cpu.inst 301 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::cpu.data 168 # number of demand (read+write) misses
system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
system.cpu.l2cache.overall_misses::cpu.inst 301 # number of overall misses
system.cpu.l2cache.overall_misses::cpu.data 168 # number of overall misses
system.cpu.l2cache.overall_misses::total 469 # number of overall misses
system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 20740000 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7180750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadReq_miss_latency::total 27920750 # number of ReadReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5181250 # number of ReadExReq miss cycles
system.cpu.l2cache.ReadExReq_miss_latency::total 5181250 # number of ReadExReq miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.inst 20740000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::cpu.data 12362000 # number of demand (read+write) miss cycles
system.cpu.l2cache.demand_miss_latency::total 33102000 # number of demand (read+write) miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.inst 20740000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::cpu.data 12362000 # number of overall miss cycles
system.cpu.l2cache.overall_miss_latency::total 33102000 # number of overall miss cycles
system.cpu.l2cache.ReadReq_accesses::cpu.inst 302 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::cpu.data 95 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadReq_accesses::total 397 # number of ReadReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::cpu.data 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.ReadExReq_accesses::total 73 # number of ReadExReq accesses(hits+misses)
system.cpu.l2cache.demand_accesses::cpu.inst 302 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::cpu.data 168 # number of demand (read+write) accesses
system.cpu.l2cache.demand_accesses::total 470 # number of demand (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.inst 302 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::cpu.data 168 # number of overall (read+write) accesses
system.cpu.l2cache.overall_accesses::total 470 # number of overall (read+write) accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.996689 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_miss_rate::total 0.997481 # miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
system.cpu.l2cache.demand_miss_rate::cpu.inst 0.996689 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
system.cpu.l2cache.demand_miss_rate::total 0.997872 # miss rate for demand accesses
system.cpu.l2cache.overall_miss_rate::cpu.inst 0.996689 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
system.cpu.l2cache.overall_miss_rate::total 0.997872 # miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68903.654485 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 75586.842105 # average ReadReq miss latency
system.cpu.l2cache.ReadReq_avg_miss_latency::total 70506.944444 # average ReadReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 70976.027397 # average ReadExReq miss latency
system.cpu.l2cache.ReadExReq_avg_miss_latency::total 70976.027397 # average ReadExReq miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
system.cpu.l2cache.demand_avg_miss_latency::total 70579.957356 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68903.654485 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::cpu.data 73583.333333 # average overall miss latency
system.cpu.l2cache.overall_avg_miss_latency::total 70579.957356 # average overall miss latency
system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.l2cache.fast_writes 0 # number of fast writes performed
system.cpu.l2cache.cache_copies 0 # number of cache copies performed
system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadReq_mshr_misses::total 396 # number of ReadReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.ReadExReq_mshr_misses::total 73 # number of ReadExReq MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.inst 301 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 16969500 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5998750 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22968250 # number of ReadReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4278250 # number of ReadExReq MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 16969500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10277000 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.demand_mshr_miss_latency::total 27246500 # number of demand (read+write) MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 16969500 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10277000 # number of overall MSHR miss cycles
system.cpu.l2cache.overall_mshr_miss_latency::total 27246500 # number of overall MSHR miss cycles
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.997481 # mshr miss rate for ReadReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
system.cpu.l2cache.demand_mshr_miss_rate::total 0.997872 # mshr miss rate for demand accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996689 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
system.cpu.l2cache.overall_mshr_miss_rate::total 0.997872 # mshr miss rate for overall accesses
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56377.076412 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 63144.736842 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 58000.631313 # average ReadReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 58606.164384 # average ReadExReq mshr miss latency
system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 58606.164384 # average ReadExReq mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56377.076412 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 61172.619048 # average overall mshr miss latency
system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58094.882729 # average overall mshr miss latency
system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
system.cpu.dcache.tags.replacements 0 # number of replacements
system.cpu.dcache.tags.tagsinuse 103.396801 # Cycle average of tags in use
system.cpu.dcache.tags.total_refs 1601 # Total number of references to valid blocks.
system.cpu.dcache.tags.sampled_refs 168 # Sample count of references to valid blocks.
system.cpu.dcache.tags.avg_refs 9.529762 # Average number of references to valid blocks.
system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
system.cpu.dcache.tags.occ_blocks::cpu.data 103.396801 # Average occupied blocks per requestor
system.cpu.dcache.tags.occ_percent::cpu.data 0.025243 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_percent::total 0.025243 # Average percentage of cache occupancy
system.cpu.dcache.tags.occ_task_id_blocks::1024 168 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::0 40 # Occupied blocks per task id
system.cpu.dcache.tags.age_task_id_blocks_1024::1 128 # Occupied blocks per task id
system.cpu.dcache.tags.occ_task_id_percent::1024 0.041016 # Percentage of cache occupancy per task id
system.cpu.dcache.tags.tag_accesses 4264 # Number of tag accesses
system.cpu.dcache.tags.data_accesses 4264 # Number of data accesses
system.cpu.dcache.ReadReq_hits::cpu.data 1086 # number of ReadReq hits
system.cpu.dcache.ReadReq_hits::total 1086 # number of ReadReq hits
system.cpu.dcache.WriteReq_hits::cpu.data 515 # number of WriteReq hits
system.cpu.dcache.WriteReq_hits::total 515 # number of WriteReq hits
system.cpu.dcache.demand_hits::cpu.data 1601 # number of demand (read+write) hits
system.cpu.dcache.demand_hits::total 1601 # number of demand (read+write) hits
system.cpu.dcache.overall_hits::cpu.data 1601 # number of overall hits
system.cpu.dcache.overall_hits::total 1601 # number of overall hits
system.cpu.dcache.ReadReq_misses::cpu.data 97 # number of ReadReq misses
system.cpu.dcache.ReadReq_misses::total 97 # number of ReadReq misses
system.cpu.dcache.WriteReq_misses::cpu.data 350 # number of WriteReq misses
system.cpu.dcache.WriteReq_misses::total 350 # number of WriteReq misses
system.cpu.dcache.demand_misses::cpu.data 447 # number of demand (read+write) misses
system.cpu.dcache.demand_misses::total 447 # number of demand (read+write) misses
system.cpu.dcache.overall_misses::cpu.data 447 # number of overall misses
system.cpu.dcache.overall_misses::total 447 # number of overall misses
system.cpu.dcache.ReadReq_miss_latency::cpu.data 7625750 # number of ReadReq miss cycles
system.cpu.dcache.ReadReq_miss_latency::total 7625750 # number of ReadReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::cpu.data 22645250 # number of WriteReq miss cycles
system.cpu.dcache.WriteReq_miss_latency::total 22645250 # number of WriteReq miss cycles
system.cpu.dcache.demand_miss_latency::cpu.data 30271000 # number of demand (read+write) miss cycles
system.cpu.dcache.demand_miss_latency::total 30271000 # number of demand (read+write) miss cycles
system.cpu.dcache.overall_miss_latency::cpu.data 30271000 # number of overall miss cycles
system.cpu.dcache.overall_miss_latency::total 30271000 # number of overall miss cycles
system.cpu.dcache.ReadReq_accesses::cpu.data 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.ReadReq_accesses::total 1183 # number of ReadReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses)
system.cpu.dcache.demand_accesses::cpu.data 2048 # number of demand (read+write) accesses
system.cpu.dcache.demand_accesses::total 2048 # number of demand (read+write) accesses
system.cpu.dcache.overall_accesses::cpu.data 2048 # number of overall (read+write) accesses
system.cpu.dcache.overall_accesses::total 2048 # number of overall (read+write) accesses
system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_miss_rate::total 0.081995 # miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_miss_rate::total 0.404624 # miss rate for WriteReq accesses
system.cpu.dcache.demand_miss_rate::cpu.data 0.218262 # miss rate for demand accesses
system.cpu.dcache.demand_miss_rate::total 0.218262 # miss rate for demand accesses
system.cpu.dcache.overall_miss_rate::cpu.data 0.218262 # miss rate for overall accesses
system.cpu.dcache.overall_miss_rate::total 0.218262 # miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 78615.979381 # average ReadReq miss latency
system.cpu.dcache.ReadReq_avg_miss_latency::total 78615.979381 # average ReadReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64700.714286 # average WriteReq miss latency
system.cpu.dcache.WriteReq_avg_miss_latency::total 64700.714286 # average WriteReq miss latency
system.cpu.dcache.demand_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
system.cpu.dcache.demand_avg_miss_latency::total 67720.357942 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::cpu.data 67720.357942 # average overall miss latency
system.cpu.dcache.overall_avg_miss_latency::total 67720.357942 # average overall miss latency
system.cpu.dcache.blocked_cycles::no_mshrs 476 # number of cycles access was blocked
system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.blocked::no_mshrs 26 # number of cycles access was blocked
system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
system.cpu.dcache.avg_blocked_cycles::no_mshrs 18.307692 # average number of cycles each access was blocked
system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
system.cpu.dcache.fast_writes 0 # number of fast writes performed
system.cpu.dcache.cache_copies 0 # number of cache copies performed
system.cpu.dcache.ReadReq_mshr_hits::cpu.data 2 # number of ReadReq MSHR hits
system.cpu.dcache.ReadReq_mshr_hits::total 2 # number of ReadReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::cpu.data 277 # number of WriteReq MSHR hits
system.cpu.dcache.WriteReq_mshr_hits::total 277 # number of WriteReq MSHR hits
system.cpu.dcache.demand_mshr_hits::cpu.data 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.demand_mshr_hits::total 279 # number of demand (read+write) MSHR hits
system.cpu.dcache.overall_mshr_hits::cpu.data 279 # number of overall MSHR hits
system.cpu.dcache.overall_mshr_hits::total 279 # number of overall MSHR hits
system.cpu.dcache.ReadReq_mshr_misses::cpu.data 95 # number of ReadReq MSHR misses
system.cpu.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::cpu.data 73 # number of WriteReq MSHR misses
system.cpu.dcache.WriteReq_mshr_misses::total 73 # number of WriteReq MSHR misses
system.cpu.dcache.demand_mshr_misses::cpu.data 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.demand_mshr_misses::total 168 # number of demand (read+write) MSHR misses
system.cpu.dcache.overall_mshr_misses::cpu.data 168 # number of overall MSHR misses
system.cpu.dcache.overall_mshr_misses::total 168 # number of overall MSHR misses
system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7282250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_latency::total 7282250 # number of ReadReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5258750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.WriteReq_mshr_miss_latency::total 5258750 # number of WriteReq MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12541000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.demand_mshr_miss_latency::total 12541000 # number of demand (read+write) MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12541000 # number of overall MSHR miss cycles
system.cpu.dcache.overall_mshr_miss_latency::total 12541000 # number of overall MSHR miss cycles
system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.080304 # mshr miss rate for ReadReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.084393 # mshr miss rate for WriteReq accesses
system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.demand_mshr_miss_rate::total 0.082031 # mshr miss rate for demand accesses
system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.overall_mshr_miss_rate::total 0.082031 # mshr miss rate for overall accesses
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76655.263158 # average ReadReq mshr miss latency
system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76655.263158 # average ReadReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 72037.671233 # average WriteReq mshr miss latency
system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 72037.671233 # average WriteReq mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
system.cpu.dcache.demand_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 74648.809524 # average overall mshr miss latency
system.cpu.dcache.overall_avg_mshr_miss_latency::total 74648.809524 # average overall mshr miss latency
system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
---------- End Simulation Statistics ----------