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Merge zizzer:/m5/Bitkeeper/m5

Browse source 
into zamp.eecs.umich.edu:/amd/brio/y/rdreslin/m5bk/unclean

--HG--
extra : convert_revision : e388676c83f75c5f19d58b5ed42d41942ff5e2cb
This commit is contained in:
Ron Dreslinski 2003-11-02 20:56:41 -05:00
commit 34c1ae0e5d
6 changed files with 194 additions and 57 deletions
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63
arch/alpha/isa_desc
View file

@ -28,12 +28,11 @@ let {{
#include "cpu/simple_cpu/simple_cpu.hh" #include "cpu/simple_cpu/simple_cpu.hh"
#include "cpu/static_inst.hh" #include "cpu/static_inst.hh"
#include "sim/annotation.hh" #include "sim/annotation.hh"
#include "sim/serialize.hh" #include "sim/sim_exit.hh"
#include "sim/sim_events.hh"
#include "sim/sim_stats.hh"
#ifdef FULL_SYSTEM #ifdef FULL_SYSTEM
#include "targetarch/ev5.hh" #include "arch/alpha/ev5.hh"
#include "arch/alpha/pseudo_inst.hh"
#endif #endif
namespace AlphaISA; namespace AlphaISA;
@ -2429,62 +2428,28 @@ decode OPCODE default Unknown::unknown() {
}}, No_OpClass); }}, No_OpClass);
0x20: m5exit_old({{ 0x20: m5exit_old({{
if (!xc->misspeculating()) if (!xc->misspeculating())
SimExit(curTick, "m5_exit_old instruction encountered"); AlphaPseudo::m5exit_old(xc);
}}, No_OpClass); }}, No_OpClass);
0x21: m5exit({{ 0x21: m5exit({{
if (!xc->misspeculating()) { if (!xc->misspeculating())
Tick delay = xc->regs.intRegFile[16]; AlphaPseudo::m5exit(xc);
Tick when = curTick + NS2Ticks(delay);
SimExit(when, "m5_exit instruction encountered");
}
}}, No_OpClass); }}, No_OpClass);
0x30: initparam({{ Ra = xc->cpu->system->init_param; }}); 0x30: initparam({{ Ra = xc->cpu->system->init_param; }});
0x40: resetstats({{ 0x40: resetstats({{
if (!xc->misspeculating()) { if (!xc->misspeculating())
using namespace Statistics; AlphaPseudo::resetstats(xc);
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Reset, when, repeat);
}
}}); }});
0x41: dumpstats({{ 0x41: dumpstats({{
if (!xc->misspeculating()) { if (!xc->misspeculating())
using namespace Statistics; AlphaPseudo::dumpstats(xc);
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Dump, when, repeat);
}
}}); }});
0x42: dumpresetstats({{ 0x42: dumpresetstats({{
if (!xc->misspeculating()) { if (!xc->misspeculating())
using namespace Statistics; AlphaPseudo::dumpresetstats(xc);
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Dump|Reset, when, repeat);
}
}}); }});
0x43: m5checkpoint({{ 0x43: m5checkpoint({{
if (!xc->misspeculating()) { if (!xc->misspeculating())
Tick delay = xc->regs.intRegFile[16]; AlphaPseudo::m5checkpoint(xc);
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupCheckpoint(when, repeat);
}
}}); }});
} }
} }

138
arch/alpha/pseudo_inst.cc Normal file
View file

@ -0,0 +1,138 @@
/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include <string>
#include "arch/alpha/pseudo_inst.hh"
#include "cpu/exec_context.hh"
#include "sim/param.hh"
#include "sim/serialize.hh"
#include "sim/sim_exit.hh"
#include "sim/sim_stats.hh"
using namespace std;
using namespace Statistics;
namespace AlphaPseudo
{
bool doStatisticsInsts;
bool doCheckpointInsts;
void
m5exit_old(ExecContext *xc)
{
SimExit(curTick, "m5_exit_old instruction encountered");
}
void
m5exit(ExecContext *xc)
{
Tick delay = xc->regs.intRegFile[16];
Tick when = curTick + NS2Ticks(delay);
SimExit(when, "m5_exit instruction encountered");
}
void
resetstats(ExecContext *xc)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Reset, when, repeat);
}
void
dumpstats(ExecContext *xc)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Dump, when, repeat);
}
void
dumpresetstats(ExecContext *xc)
{
if (!doStatisticsInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupEvent(Dump|Reset, when, repeat);
}
void
m5checkpoint(ExecContext *xc)
{
if (!doCheckpointInsts)
return;
Tick delay = xc->regs.intRegFile[16];
Tick period = xc->regs.intRegFile[17];
Tick when = curTick + NS2Ticks(delay);
Tick repeat = NS2Ticks(period);
SetupCheckpoint(when, repeat);
}
class Context : public ParamContext
{
public:
Context(const string &section) : ParamContext(section) {}
void checkParams();
};
Context context("PseudoInsts");
Param<bool> __statistics(&context, "statistics", "yes");
Param<bool> __checkpoint(&context, "checkpoint", "yes");
void
Context::checkParams()
{
doStatisticsInsts = __statistics;
doCheckpointInsts = __checkpoint;
}
}

39
arch/alpha/pseudo_inst.hh Normal file
View file

@ -0,0 +1,39 @@
/*
* Copyright (c) 2003 The Regents of The University of Michigan
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
class ExecContext;
namespace AlphaPseudo
{
void m5exit(ExecContext *xc);
void m5exit_old(ExecContext *xc);
void resetstats(ExecContext *xc);
void dumpstats(ExecContext *xc);
void dumpresetstats(ExecContext *xc);
void m5checkpoint(ExecContext *xc);
}

6
sim/sim_events.cc
View file

@ -63,12 +63,6 @@ SimExitEvent::description()
return "simulation termination"; return "simulation termination";
} }
void
SimExit(Tick when, const char *message)
{
static SimExitEvent event(when, message);
}
// //
// constructor: automatically schedules at specified time // constructor: automatically schedules at specified time
// //

2
sim/sim_events.hh
View file

@ -66,8 +66,6 @@ class SimExitEvent : public Event
virtual const char *description(); virtual const char *description();
}; };
void SimExit(Tick when, const char *message);
// //
// Event class to terminate simulation after 'n' related events have // Event class to terminate simulation after 'n' related events have
// occurred using a shared counter: used to terminate when *all* // occurred using a shared counter: used to terminate when *all*

3
sim/sim_exit.hh
View file

@ -31,11 +31,14 @@
#include <string> #include <string>
#include "sim/host.hh"
class Callback; class Callback;
void registerExitCallback(Callback *); void registerExitCallback(Callback *);
void exitNow(const std::string &cause, int exit_code); void exitNow(const std::string &cause, int exit_code);
void exitNow(const char *cause, int exit_code); void exitNow(const char *cause, int exit_code);
void SimExit(Tick when, const char *message);
#endif // __SIM_EXIT_HH__ #endif // __SIM_EXIT_HH__