dev: seperate legacy io offsets from PCI offset
The PC platform has a single IO range that is used both legacy IO and PCI IO while other platforms may use seperate regions. Provide another mechanism to configure the legacy IO base address range and set it to the PCI IO address range for x86.
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1c0ae90027
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346fe73370
3 changed files with 3 additions and 1 deletions
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@ -98,6 +98,7 @@ class PciDevice(DmaDevice):
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BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
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BAR3LegacyIO = Param.Bool(False, "Whether BAR3 is hardwired legacy IO")
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BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
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BAR4LegacyIO = Param.Bool(False, "Whether BAR4 is hardwired legacy IO")
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BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
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BAR5LegacyIO = Param.Bool(False, "Whether BAR5 is hardwired legacy IO")
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LegacyIOBase = Param.Addr(0x0, "Base Address for Legacy IO")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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CardbusCIS = Param.UInt32(0x00, "Cardbus Card Information Structure")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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SubsystemID = Param.UInt16(0x00, "Subsystem ID")
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@ -213,7 +213,7 @@ PciDevice::PciDevice(const Params *p)
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for (int i = 0; i < 6; ++i) {
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for (int i = 0; i < 6; ++i) {
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if (legacyIO[i]) {
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if (legacyIO[i]) {
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BARAddrs[i] = platform->calcPciIOAddr(letoh(config.baseAddr[i]));
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BARAddrs[i] = p->LegacyIOBase + letoh(config.baseAddr[i]);
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config.baseAddr[i] = 0;
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config.baseAddr[i] = 0;
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} else {
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} else {
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BARAddrs[i] = 0;
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BARAddrs[i] = 0;
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@ -84,6 +84,7 @@ class SouthBridge(SimObject):
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ide.ProgIF = 0x80
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ide.ProgIF = 0x80
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ide.InterruptLine = 14
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ide.InterruptLine = 14
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ide.InterruptPin = 1
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ide.InterruptPin = 1
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ide.LegacyIOBase = x86IOAddress(0)
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def attachIO(self, bus, dma_ports):
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def attachIO(self, bus, dma_ports):
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# Route interupt signals
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# Route interupt signals
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