Remove mem parameter. Should have been removed earlier.
src/python/m5/objects/BaseCPU.py: These parameters should have been removed in an earlier push. --HG-- extra : convert_revision : 781b39ca370361e9568b1af0be96ff5848b1f3f4
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@ -8,7 +8,6 @@ from Bus import Bus
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class BaseCPU(SimObject):
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class BaseCPU(SimObject):
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type = 'BaseCPU'
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type = 'BaseCPU'
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abstract = True
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abstract = True
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mem = Param.MemObject("memory")
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system = Param.System(Parent.any, "system object")
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system = Param.System(Parent.any, "system object")
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cpu_id = Param.Int("CPU identifier")
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cpu_id = Param.Int("CPU identifier")
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@ -47,7 +46,6 @@ class BaseCPU(SimObject):
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self.icache_port = ic.cpu_side
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self.icache_port = ic.cpu_side
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self.dcache_port = dc.cpu_side
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self.dcache_port = dc.cpu_side
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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self._mem_ports = ['icache.mem_side', 'dcache.mem_side']
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# self.mem = dc
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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def addTwoLevelCacheHierarchy(self, ic, dc, l2c):
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self.addPrivateSplitL1Caches(ic, dc)
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self.addPrivateSplitL1Caches(ic, dc)
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