ARM: Implement all integer multiply instructions.
This commit is contained in:
Gabe Black
parent
50229be27f
commit
33da368e99
3 changed files with 370 additions and 0 deletions
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@ -57,3 +57,6 @@
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//Branches
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//Branches
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##include "branch.isa"
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##include "branch.isa"
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//Multiply
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##include "mult.isa"
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359
src/arch/arm/isa/insts/mult.isa
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359
src/arch/arm/isa/insts/mult.isa
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@ -0,0 +1,359 @@
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// -*- mode:c++ -*-
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// Copyright (c) 2010 ARM Limited
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// All rights reserved
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//
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// The license below extends only to copyright in the software and shall
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// not be construed as granting a license to any other intellectual
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// property including but not limited to intellectual property relating
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// to a hardware implementation of the functionality of the software
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// licensed hereunder. You may use the software subject to the license
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// terms below provided that you ensure that this notice is replicated
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// unmodified and in its entirety in all distributions of the software,
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// modified or unmodified, in source code or in binary form.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are
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// met: redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer;
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// redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution;
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// neither the name of the copyright holders nor the names of its
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// contributors may be used to endorse or promote products derived from
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// this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// Authors: Gabe Black
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let {{
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header_output = ""
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decoder_output = ""
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exec_output = ""
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calcQCode = '''
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cprintf("canOverflow: %%d\\n", Reg0 < resTemp);
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replaceBits(CondCodes, 27, Reg0 < resTemp);
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'''
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calcCcCode = '''
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uint16_t _iz, _in;
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_in = (resTemp >> %(negBit)d) & 1;
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_iz = ((%(zType)s)resTemp == 0);
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CondCodes = _in << 31 | _iz << 30 | (CondCodes & 0x3FFFFFFF);
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DPRINTF(Arm, "(in, iz) = (%%d, %%d)\\n", _in, _iz);
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'''
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def buildMultInst(mnem, doCc, unCc, regs, code, flagType):
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global header_output, decoder_output, exec_output
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cCode = carryCode[flagType]
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vCode = overflowCode[flagType]
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zType = "uint32_t"
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negBit = 31
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if flagType == "llbit":
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zType = "uint64_t"
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negBit = 63
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if flagType == "overflow":
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ccCode = calcQCode
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else:
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ccCode = calcCcCode % {
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"negBit": negBit,
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"zType": zType
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}
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if not regs in (3, 4):
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raise Exception, "Multiplication instructions with %d " + \
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"registers are not implemented"
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if regs == 3:
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base = 'Mult3'
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else:
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base = 'Mult4'
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Name = "New" + mnem.capitalize()
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if unCc:
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iop = InstObjParams(mnem, Name, base,
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{"code" : code,
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"predicate_test": predicateTest})
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if doCc:
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iopCc = InstObjParams(mnem + "s", Name + "Cc", base,
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{"code" : code + ccCode,
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"predicate_test": predicateTest})
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if regs == 3:
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declare = Mult3Declare
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constructor = Mult3Constructor
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else:
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declare = Mult4Declare
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constructor = Mult4Constructor
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if unCc:
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header_output += declare.subst(iop)
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decoder_output += constructor.subst(iop)
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exec_output += PredOpExecute.subst(iop)
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if doCc:
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header_output += declare.subst(iopCc)
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decoder_output += constructor.subst(iopCc)
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exec_output += PredOpExecute.subst(iopCc)
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def buildMult3Inst(mnem, code, flagType = "logic"):
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buildMultInst(mnem, True, True, 3, code, flagType)
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def buildMult3InstCc(mnem, code, flagType = "logic"):
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buildMultInst(mnem, True, False, 3, code, flagType)
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def buildMult3InstUnCc(mnem, code, flagType = "logic"):
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buildMultInst(mnem, False, True, 3, code, flagType)
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def buildMult4Inst(mnem, code, flagType = "logic"):
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buildMultInst(mnem, True, True, 4, code, flagType)
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def buildMult4InstCc(mnem, code, flagType = "logic"):
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buildMultInst(mnem, True, False, 4, code, flagType)
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def buildMult4InstUnCc(mnem, code, flagType = "logic"):
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buildMultInst(mnem, False, True, 4, code, flagType)
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buildMult4Inst ("mla", "Reg0 = resTemp = Reg1 * Reg2 + Reg3;")
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buildMult4InstUnCc("mls", "Reg0 = resTemp = Reg3 - Reg1 * Reg2;")
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buildMult3Inst ("mul", "Reg0 = resTemp = Reg1 * Reg2;")
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buildMult4InstCc ("smlabb", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 15, 0)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smlabt", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 31, 16)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smlatb", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 15, 0)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smlatt", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 31, 16)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smlad", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 31, 16)) +
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 15, 0)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smladx", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 15, 0)) +
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 31, 16)) +
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Reg3.sw;
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''', "overflow")
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buildMult4Inst ("smlal", '''resTemp = sext<32>(Reg2) * sext<32>(Reg3) +
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(int64_t)((Reg1.ud << 32) | Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''', "llbit")
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buildMult4InstUnCc("smlalbb", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 15, 0)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlalbt", '''resTemp = sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 31, 16)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlaltb", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 15, 0)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlaltt", '''resTemp = sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 31, 16)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlald", '''resTemp =
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sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 31, 16)) +
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sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 15, 0)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlaldx", '''resTemp =
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sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 15, 0)) +
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sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 31, 16)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstCc ("smlawb", '''Reg0 = resTemp =
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(Reg1.sw *
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sext<16>(bits(Reg2, 15, 0)) +
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(Reg3.sw << 16)) >> 16;
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''', "overflow")
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buildMult4InstCc ("smlawt", '''Reg0 = resTemp =
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(Reg1.sw *
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sext<16>(bits(Reg2, 31, 16)) +
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(Reg3.sw << 16)) >> 16;
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''', "overflow")
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buildMult4InstCc ("smlsd", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 15, 0)) -
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 31, 16)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstCc ("smlsdx", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 31, 16)) -
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 15, 0)) +
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Reg3.sw;
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''', "overflow")
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buildMult4InstUnCc("smlsld", '''resTemp =
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sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 15, 0)) -
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sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 31, 16)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smlsldx", '''resTemp =
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sext<16>(bits(Reg2, 15, 0)) *
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sext<16>(bits(Reg3, 31, 16)) -
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sext<16>(bits(Reg2, 31, 16)) *
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sext<16>(bits(Reg3, 15, 0)) +
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(int64_t)((Reg1.ud << 32) |
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Reg0.ud);
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Reg0.ud = (uint32_t)resTemp;
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Reg1.ud = (uint32_t)(resTemp >> 32);
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''')
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buildMult4InstUnCc("smmla", '''Reg0 = resTemp =
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((int64_t)(Reg3.ud << 32) +
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Reg1.sw * Reg2.sw) >> 32;
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''')
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buildMult4InstUnCc("smmlar", '''Reg0 = resTemp =
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((int64_t)(Reg3.ud << 32) +
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Reg1.sw * Reg2.sw +
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ULL(0x80000000)) >> 32;
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''')
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buildMult4InstUnCc("smmls", '''Reg0 = resTemp =
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((int64_t)(Reg3.ud << 32) -
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Reg1.sw * Reg2.sw) >> 32;
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''')
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buildMult4InstUnCc("smmlsr", '''Reg0 = resTemp =
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((int64_t)(Reg3.ud << 32) -
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Reg1.sw * Reg2.sw +
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ULL(0x80000000)) >> 32;
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''')
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buildMult3InstUnCc("smmul", '''Reg0 = resTemp =
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((int64_t)Reg1 *
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(int64_t)Reg2) >> 32;
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''')
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buildMult3InstUnCc("smmulr", '''Reg0 = resTemp =
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((int64_t)Reg1 *
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(int64_t)Reg2 +
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ULL(0x80000000)) >> 32;
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''')
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buildMult3InstCc ("smuad", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 15, 0)) +
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 31, 16));
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''', "overflow")
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buildMult3InstCc ("smuadx", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 31, 16)) +
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 15, 0));
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''', "overflow")
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buildMult3InstUnCc("smulbb", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 15, 0));
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''')
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buildMult3InstUnCc("smulbt", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 15, 0));
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''')
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buildMult3InstUnCc("smultb", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 15, 0)) *
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sext<16>(bits(Reg2, 31, 16));
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''')
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buildMult3InstUnCc("smultt", '''Reg0 = resTemp =
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sext<16>(bits(Reg1, 31, 16)) *
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sext<16>(bits(Reg2, 31, 16));
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''')
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buildMult4Inst ("smull", '''resTemp = Reg2.sw * Reg3.sw;
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Reg0 = (int32_t)resTemp;
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Reg1 = (int32_t)(resTemp >> 32);
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''', "llbit")
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buildMult3InstUnCc("smulwb", '''Reg0 = resTemp =
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(Reg1.sw *
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sext<16>(bits(Reg2, 15, 0))) >> 16;
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||||||
|
''')
|
||||||
|
buildMult3InstUnCc("smulwt", '''Reg0 = resTemp =
|
||||||
|
(Reg1.sw *
|
||||||
|
sext<16>(bits(Reg2, 31, 16))) >> 16;
|
||||||
|
''')
|
||||||
|
buildMult3InstUnCc("smusd", '''Reg0 = resTemp =
|
||||||
|
sext<16>(bits(Reg1, 15, 0)) *
|
||||||
|
sext<16>(bits(Reg2, 15, 0)) -
|
||||||
|
sext<16>(bits(Reg1, 31, 16)) *
|
||||||
|
sext<16>(bits(Reg2, 31, 16));
|
||||||
|
''')
|
||||||
|
buildMult3InstUnCc("smusdx", '''Reg0 = resTemp =
|
||||||
|
sext<16>(bits(Reg1, 15, 0)) *
|
||||||
|
sext<16>(bits(Reg2, 31, 16)) -
|
||||||
|
sext<16>(bits(Reg1, 31, 16)) *
|
||||||
|
sext<16>(bits(Reg2, 15, 0));
|
||||||
|
''')
|
||||||
|
buildMult4InstUnCc("umaal", '''resTemp = Reg2.ud * Reg3.ud +
|
||||||
|
Reg0.ud + Reg1.ud;
|
||||||
|
Reg0.ud = (uint32_t)resTemp;
|
||||||
|
Reg1.ud = (uint32_t)(resTemp >> 32);
|
||||||
|
''')
|
||||||
|
buildMult4Inst ("umlal", '''resTemp = Reg2.ud * Reg3.ud + Reg0.ud +
|
||||||
|
(Reg1.ud << 32);
|
||||||
|
Reg0.ud = (uint32_t)resTemp;
|
||||||
|
Reg1.ud = (uint32_t)(resTemp >> 32);
|
||||||
|
''', "llbit")
|
||||||
|
buildMult4Inst ("umull", '''resTemp = Reg2.ud * Reg3.ud;
|
||||||
|
Reg0 = (uint32_t)resTemp;
|
||||||
|
Reg1 = (uint32_t)(resTemp >> 32);
|
||||||
|
''', "llbit")
|
||||||
|
}};
|
||||||
|
|
@ -89,6 +89,14 @@ def operands {{
|
||||||
maybePCRead, maybePCWrite),
|
maybePCRead, maybePCWrite),
|
||||||
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
|
'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
|
||||||
maybePCRead, maybePCWrite),
|
maybePCRead, maybePCWrite),
|
||||||
|
'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
|
||||||
|
maybePCRead, maybePCWrite),
|
||||||
|
'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7,
|
||||||
|
maybePCRead, maybePCWrite),
|
||||||
|
'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8,
|
||||||
|
maybePCRead, maybePCWrite),
|
||||||
|
'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9,
|
||||||
|
maybePCRead, maybePCWrite),
|
||||||
#General Purpose Integer Reg Operands
|
#General Purpose Integer Reg Operands
|
||||||
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
|
'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
|
||||||
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
|
'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
|
||||||
|
|
|
||||||
Loading…
Reference in a new issue