X86: Use suffixes to differentiate XMM/MMX/GPR operands.
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3a4438a868
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33cb4c2f09
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@ -58,16 +58,16 @@ microcode = '''
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# ADDPD
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# ADDPD
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# ADDSS
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# ADDSS
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def macroop ADDSD_R_R {
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def macroop ADDSD_XMM_XMM {
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addfp xmml, xmml, xmmlm
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addfp xmml, xmml, xmmlm
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};
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};
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def macroop ADDSD_R_M {
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def macroop ADDSD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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addfp xmml, xmml, ufp1
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addfp xmml, xmml, ufp1
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};
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};
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def macroop ADDSD_R_P {
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def macroop ADDSD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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addfp xmml, xmml, ufp1
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addfp xmml, xmml, ufp1
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@ -58,16 +58,16 @@ microcode = '''
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# DIVPD
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# DIVPD
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# DIVSS
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# DIVSS
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def macroop DIVSD_R_R {
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def macroop DIVSD_XMM_XMM {
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divfp xmml, xmml, xmmlm
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divfp xmml, xmml, xmmlm
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};
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};
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def macroop DIVSD_R_M {
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def macroop DIVSD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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divfp xmml, xmml, ufp1
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divfp xmml, xmml, ufp1
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};
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};
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def macroop DIVSD_R_P {
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def macroop DIVSD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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divfp xmml, xmml, ufp1
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divfp xmml, xmml, ufp1
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@ -58,16 +58,16 @@ microcode = '''
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# MULPD
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# MULPD
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# MULSS
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# MULSS
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def macroop MULSD_R_R {
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def macroop MULSD_XMM_XMM {
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mulfp xmml, xmml, xmmlm
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mulfp xmml, xmml, xmmlm
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};
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};
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def macroop MULSD_R_M {
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def macroop MULSD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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mulfp xmml, xmml, ufp1
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mulfp xmml, xmml, ufp1
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};
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};
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def macroop MULSD_R_P {
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def macroop MULSD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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mulfp xmml, xmml, ufp1
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mulfp xmml, xmml, ufp1
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@ -58,16 +58,16 @@ microcode = '''
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# SQRTPD
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# SQRTPD
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# SQRTSS
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# SQRTSS
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def macroop SQRTSD_R_R {
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def macroop SQRTSD_XMM_XMM {
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sqrtfp xmml, xmml, xmmlm
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sqrtfp xmml, xmml, xmmlm
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};
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};
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def macroop SQRTSD_R_M {
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def macroop SQRTSD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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sqrtfp xmml, xmml, ufp1
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sqrtfp xmml, xmml, ufp1
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};
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};
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def macroop SQRTSD_R_P {
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def macroop SQRTSD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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sqrtfp xmml, xmml, ufp1
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sqrtfp xmml, xmml, ufp1
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@ -58,16 +58,16 @@ microcode = '''
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# SUBPD
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# SUBPD
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# SUBSS
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# SUBSS
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def macroop SUBSD_R_R {
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def macroop SUBSD_XMM_XMM {
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subfp xmml, xmml, xmmlm
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subfp xmml, xmml, xmmlm
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};
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};
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def macroop SUBSD_R_M {
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def macroop SUBSD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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subfp xmml, xmml, ufp1
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subfp xmml, xmml, ufp1
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};
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};
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def macroop SUBSD_R_P {
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def macroop SUBSD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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subfp xmml, xmml, ufp1
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subfp xmml, xmml, ufp1
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@ -58,16 +58,16 @@ microcode = '''
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# COMISD
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# COMISD
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# UCOMISS
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# UCOMISS
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def macroop UCOMISD_R_R {
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def macroop UCOMISD_XMM_XMM {
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compfp xmml, xmmlm
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compfp xmml, xmmlm
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};
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};
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def macroop UCOMISD_R_M {
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def macroop UCOMISD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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compfp xmml, ufp1
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compfp xmml, ufp1
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};
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};
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def macroop UCOMISD_R_P {
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def macroop UCOMISD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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compfp xmml, ufp1
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compfp xmml, ufp1
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@ -58,7 +58,7 @@ microcode = '''
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# CVTSD2SI
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# CVTSD2SI
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# CVTTSS2SI
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# CVTTSS2SI
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def macroop CVTTSD2SI_R_R {
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def macroop CVTTSD2SI_R_XMM {
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cvtf_d2i reg, xmmlm
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cvtf_d2i reg, xmmlm
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};
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};
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@ -54,33 +54,33 @@
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# Authors: Gabe Black
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# Authors: Gabe Black
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microcode = '''
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microcode = '''
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def macroop MOVAPS_R_M {
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def macroop MOVAPS_XMM_M {
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# Check low address.
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# Check low address.
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ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
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ldfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
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ldfp xmml, seg, sib, disp, dataSize=8
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ldfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVAPS_R_P {
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def macroop MOVAPS_XMM_P {
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rdip t7
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rdip t7
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# Check low address.
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# Check low address.
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ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
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ldfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
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ldfp xmml, seg, riprel, disp, dataSize=8
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ldfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVAPS_M_R {
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def macroop MOVAPS_M_XMM {
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# Check low address.
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# Check low address.
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stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
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stfp xmmh, seg, sib, "DISPLACEMENT + 8", dataSize=8
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stfp xmml, seg, sib, disp, dataSize=8
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stfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVAPS_P_R {
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def macroop MOVAPS_P_XMM {
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rdip t7
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rdip t7
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# Check low address.
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# Check low address.
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stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
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stfp xmmh, seg, riprel, "DISPLACEMENT + 8", dataSize=8
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stfp xmml, seg, riprel, disp, dataSize=8
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stfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVAPS_R_R {
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def macroop MOVAPS_XMM_XMM {
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# Check low address.
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# Check low address.
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movfp xmml, xmmlm, dataSize=8
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movfp xmml, xmmlm, dataSize=8
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movfp xmmh, xmmhm, dataSize=8
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movfp xmmh, xmmhm, dataSize=8
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@ -93,25 +93,25 @@ def macroop MOVAPS_R_R {
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# MOVHPD
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# MOVHPD
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# MOVLPS
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# MOVLPS
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def macroop MOVLPD_R_M {
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def macroop MOVLPD_XMM_M {
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ldfp xmml, seg, sib, disp, dataSize=8
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ldfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVLPD_R_P {
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def macroop MOVLPD_XMM_P {
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rdip t7
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rdip t7
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ldfp xmml, seg, riprel, disp, dataSize=8
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ldfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVLPD_M_R {
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def macroop MOVLPD_M_XMM {
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stfp xmml, seg, sib, disp, dataSize=8
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stfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVLPD_P_R {
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def macroop MOVLPD_P_XMM {
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rdip t7
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rdip t7
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stfp xmml, seg, riprel, disp, dataSize=8
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stfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVLPD_R_R {
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def macroop MOVLPD_XMM_XMM {
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movfp xmml, xmmlm, dataSize=8
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movfp xmml, xmmlm, dataSize=8
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};
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};
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@ -119,27 +119,27 @@ def macroop MOVLPD_R_R {
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# MOVLHPS
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# MOVLHPS
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# MOVSS
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# MOVSS
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def macroop MOVSD_R_M {
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def macroop MOVSD_XMM_M {
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# Zero xmmh
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# Zero xmmh
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ldfp xmml, seg, sib, disp, dataSize=8
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ldfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVSD_R_P {
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def macroop MOVSD_XMM_P {
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rdip t7
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rdip t7
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# Zero xmmh
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# Zero xmmh
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ldfp xmml, seg, riprel, disp, dataSize=8
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ldfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVSD_M_R {
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def macroop MOVSD_M_XMM {
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stfp xmml, seg, sib, disp, dataSize=8
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stfp xmml, seg, sib, disp, dataSize=8
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};
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};
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def macroop MOVSD_P_R {
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def macroop MOVSD_P_XMM {
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rdip t7
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rdip t7
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stfp xmml, seg, riprel, disp, dataSize=8
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stfp xmml, seg, riprel, disp, dataSize=8
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};
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};
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def macroop MOVSD_R_R {
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def macroop MOVSD_XMM_XMM {
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movfp xmml, xmmlm, dataSize=8
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movfp xmml, xmmlm, dataSize=8
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};
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};
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'''
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'''
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@ -56,19 +56,19 @@
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microcode = '''
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microcode = '''
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# XORPS
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# XORPS
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def macroop XORPD_R_R {
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def macroop XORPD_XMM_XMM {
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xorfp xmml, xmml, xmmlm
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xorfp xmml, xmml, xmmlm
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xorfp xmmh, xmmh, xmmhm
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xorfp xmmh, xmmh, xmmhm
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};
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};
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def macroop XORPD_R_M {
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def macroop XORPD_XMM_M {
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ldfp ufp1, seg, sib, disp
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ldfp ufp1, seg, sib, disp
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ldfp ufp2, seg, sib, "DISPLACEMENT + 8"
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ldfp ufp2, seg, sib, "DISPLACEMENT + 8"
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xorfp xmml, xmml, ufp1
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xorfp xmml, xmml, ufp1
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xorfp xmmh, xmmh, ufp2
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xorfp xmmh, xmmh, ufp2
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};
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};
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def macroop XORPD_R_P {
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def macroop XORPD_XMM_P {
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rdip t7
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rdip t7
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ldfp ufp1, seg, riprel, disp
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ldfp ufp1, seg, riprel, disp
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ldfp ufp2, seg, riprel, "DISPLACEMENT + 8"
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ldfp ufp2, seg, riprel, "DISPLACEMENT + 8"
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@ -56,16 +56,16 @@
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microcode = '''
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microcode = '''
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# CVTSI2SS
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# CVTSI2SS
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def macroop CVTSI2SD_R_R {
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def macroop CVTSI2SD_XMM_R {
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cvtf_i2d xmml, regm
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cvtf_i2d xmml, regm
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};
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};
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def macroop CVTSI2SD_R_M {
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def macroop CVTSI2SD_XMM_M {
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ld t1, seg, sib, disp
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ld t1, seg, sib, disp
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cvtf_i2d xmml, t1
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cvtf_i2d xmml, t1
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};
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};
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def macroop CVTSI2SD_R_P {
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def macroop CVTSI2SD_XMM_P {
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rdip t7
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rdip t7
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ld t1, seg, riprel, disp
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ld t1, seg, riprel, disp
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cvtf_i2d xmml, t1
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cvtf_i2d xmml, t1
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@ -190,7 +190,12 @@ let {{
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env.addReg(ModRMRegIndex)
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env.addReg(ModRMRegIndex)
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env.addToDisassembly(
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env.addToDisassembly(
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"printReg(out, %s, regSize);\n" % ModRMRegIndex)
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"printReg(out, %s, regSize);\n" % ModRMRegIndex)
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Name += "_R"
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if opType.tag == "P":
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Name += "_MMX"
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elif opType.tag == "V":
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Name += "_XMM"
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else:
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Name += "_R"
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elif opType.tag in ("E", "Q", "W"):
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elif opType.tag in ("E", "Q", "W"):
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# This might refer to memory or to a register. We need to
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# This might refer to memory or to a register. We need to
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# divide it up farther.
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# divide it up farther.
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@ -202,9 +207,16 @@ let {{
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# modrm addressing.
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# modrm addressing.
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memEnv = copy.copy(env)
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memEnv = copy.copy(env)
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memEnv.doModRM = True
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memEnv.doModRM = True
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regSuffix = "_R"
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if opType.tag == "Q":
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regSuffix = "_MMX"
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elif opType.tag == "W":
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regSuffix = "_XMM"
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return doSplitDecode("MODRM_MOD",
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return doSplitDecode("MODRM_MOD",
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{"3" : (specializeInst, Name + "_R", copy.copy(opTypes), regEnv)},
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{"3" : (specializeInst, Name + regSuffix,
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(doRipRelativeDecode, Name, copy.copy(opTypes), memEnv))
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copy.copy(opTypes), regEnv)},
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(doRipRelativeDecode, Name,
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copy.copy(opTypes), memEnv))
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elif opType.tag in ("I", "J"):
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elif opType.tag in ("I", "J"):
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# Immediates
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# Immediates
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env.addToDisassembly(
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env.addToDisassembly(
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@ -218,7 +230,12 @@ let {{
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env.addReg(ModRMRMIndex)
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env.addReg(ModRMRMIndex)
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env.addToDisassembly(
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env.addToDisassembly(
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"printReg(out, %s, regSize);\n" % ModRMRMIndex)
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"printReg(out, %s, regSize);\n" % ModRMRMIndex)
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Name += "_R"
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if opType.tag == "PR":
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Name += "_MMX"
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elif opType.tag == "VR":
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Name += "_XMM"
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else:
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Name += "_R"
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elif opType.tag in ("X", "Y"):
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elif opType.tag in ("X", "Y"):
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# This type of memory addressing is for string instructions.
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# This type of memory addressing is for string instructions.
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# They'll use the right index and segment internally.
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# They'll use the right index and segment internally.
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