mem: Align cache timing to clock edges
This patch changes the cache timing calculations such that the results are aligned to clock edges. Plenty stats change as a results of this patch.
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10650fc525
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1 changed files with 5 additions and 5 deletions
10
src/mem/cache/cache_impl.hh
vendored
10
src/mem/cache/cache_impl.hh
vendored
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@ -929,7 +929,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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// responseLatency is the latency of the return path
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// from lower level caches/memory to an upper level cache or
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// the core.
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completion_time = curTick() + responseLatency * clockPeriod() +
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completion_time = clockEdge(responseLatency) +
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(transfer_offset ? pkt->busLastWordDelay :
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pkt->busFirstWordDelay);
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@ -946,14 +946,14 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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// responseLatency is the latency of the return path
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// from lower level caches/memory to an upper level cache or
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// the core.
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completion_time = curTick() + responseLatency * clockPeriod() +
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completion_time = clockEdge(responseLatency) +
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pkt->busLastWordDelay;
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target->pkt->req->setExtraData(0);
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} else {
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// not a cache fill, just forwarding response
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// responseLatency is the latency of the return path
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// from lower level cahces/memory to the core.
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completion_time = curTick() + responseLatency * clockPeriod() +
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completion_time = clockEdge(responseLatency) +
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pkt->busLastWordDelay;
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if (pkt->isRead() && !is_error) {
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target->pkt->setData(pkt->getPtr<uint8_t>());
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@ -1021,7 +1021,7 @@ Cache<TagStore>::recvTimingResp(PacketPtr pkt)
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}
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mq = mshr->queue;
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mq->markPending(mshr);
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requestMemSideBus((RequestCause)mq->index, curTick() +
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requestMemSideBus((RequestCause)mq->index, clockEdge() +
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pkt->busLastWordDelay);
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} else {
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mq->deallocate(mshr);
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@ -1257,7 +1257,7 @@ Cache<TagStore>::handleFill(PacketPtr pkt, BlkType *blk,
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std::memcpy(blk->data, pkt->getPtr<uint8_t>(), blkSize);
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}
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blk->whenReady = curTick() + responseLatency * clockPeriod() +
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blk->whenReady = clockEdge() + responseLatency * clockPeriod() +
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pkt->busLastWordDelay;
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return blk;
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