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Sim: Fix Simulation.py to allow more than 1 core for standard switching.

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This patch moves the assignment of testsys.switch_cpus, testsys.switch_cpus_1,
switch_cpu_list, and switch_cpu_list1 outside of the for loop so they are
assigned only once, after switch_cpus and switch_cpus_1 are constructed.
This commit is contained in:
Anthony Gutierrez 2011-04-04 11:42:31 -05:00
parent b20e92e1ca
commit 332adcdd1a
1 changed files with 9 additions and 9 deletions
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10
configs/common/Simulation.py
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@ -123,6 +123,11 @@ def run(options, root, testsys, cpu_class):
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]
if options.standard_switch:
if not options.caches:
# O3 CPU must have a cache to work.
print "O3 CPU must be used with caches"
sys.exit(1)
switch_cpus = [TimingSimpleCPU(defer_registration=True, cpu_id=(np+i))
for i in xrange(np)]
switch_cpus_1 = [DerivO3CPU(defer_registration=True, cpu_id=(2*np+i))
@ -161,11 +166,6 @@ def run(options, root, testsys, cpu_class):
if options.max_inst:
switch_cpus_1[i].max_insts_any_thread = options.max_inst
if not options.caches:
# O3 CPU must have a cache to work.
print "O3 CPU must be used with caches"
sys.exit(1)
testsys.switch_cpus = switch_cpus
testsys.switch_cpus_1 = switch_cpus_1
switch_cpu_list = [(testsys.cpu[i], switch_cpus[i]) for i in xrange(np)]