ARM: Add configuration for Linux/Full System
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2 changed files with 86 additions and 3 deletions
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@ -1,3 +1,15 @@
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# Copyright (c) 2010 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2008 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -170,6 +182,52 @@ def makeSparcSystem(mem_mode, mdesc = None):
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return self
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def makeLinuxArmSystem(mem_mode, mdesc = None, bare_metal=False,
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machine_type = None):
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if bare_metal:
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self = ArmSystem()
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else:
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self = LinuxArmSystem()
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if not mdesc:
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# generic system
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mdesc = SysConfig()
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self.readfile = mdesc.script()
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self.iobus = Bus(bus_id=0)
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self.membus = MemBus(bus_id=1)
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self.membus.badaddr_responder.warn_access = "warn"
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self.bridge = Bridge(delay='50ns', nack_delay='4ns')
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self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem()), zero = True)
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self.bridge.side_a = self.iobus.port
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self.bridge.side_b = self.membus.port
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self.physmem.port = self.membus.port
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self.mem_mode = mem_mode
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if machine_type == "RealView_PBX":
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self.realview = RealViewPBX()
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elif machine_type == "RealView_EB":
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self.realview = RealViewEB()
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else:
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print "Unknown Machine Type"
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sys.exit(1)
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if not bare_metal and machine_type:
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self.machine_type = machine_type
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elif bare_metal:
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self.realview.uart.end_on_eot = True
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self.realview.attachOnChipIO(self.membus)
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self.realview.attachIO(self.iobus)
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self.intrctrl = IntrControl()
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self.terminal = Terminal()
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self.boot_osflags = 'earlyprintk mem=128MB console=ttyAMA0 lpj=19988480 norandmaps'
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return self
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def makeLinuxMipsSystem(mem_mode, mdesc = None):
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class BaseMalta(Malta):
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ethernet = NSGigE(pci_bus=0, pci_dev=1, pci_func=0)
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@ -1,3 +1,15 @@
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# Copyright (c) 2010 ARM Limited
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# All rights reserved.
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2006-2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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@ -56,7 +68,11 @@ parser = optparse.OptionParser()
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# System options
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parser.add_option("--kernel", action="store", type="string")
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parser.add_option("--script", action="store", type="string")
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if buildEnv['TARGET_ISA'] == "arm":
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parser.add_option("--bare-metal", action="store_true",
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help="Provide the raw system without the linux specific bits")
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parser.add_option("--machine-type", action="store", type="choice",
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choices=ArmMachineType.map.keys(), default="RealView_PBX")
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# Benchmark options
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parser.add_option("--dual", action="store_true",
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help="Simulate two systems attached with an ethernet link")
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@ -112,6 +128,9 @@ elif buildEnv['TARGET_ISA'] == "sparc":
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test_sys = makeSparcSystem(test_mem_mode, bm[0])
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elif buildEnv['TARGET_ISA'] == "x86":
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test_sys = makeLinuxX86System(test_mem_mode, np, bm[0])
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elif buildEnv['TARGET_ISA'] == "arm":
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test_sys = makeLinuxArmSystem(test_mem_mode, bm[0],
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bare_metal=options.bare_metal, machine_type=options.machine_type)
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else:
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fatal("incapable of building non-alpha or non-sparc full system!")
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@ -126,9 +145,13 @@ test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
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CacheConfig.config_cache(options, test_sys)
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if options.caches or options.l2cache:
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if bm[0]:
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mem_size = bm[0].mem()
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else:
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mem_size = SysConfig().mem()
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test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
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test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')]
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test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB'))
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test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
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test_sys.iocache = IOCache(addr_range=mem_size)
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test_sys.iocache.cpu_side = test_sys.iobus.port
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test_sys.iocache.mem_side = test_sys.membus.port
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@ -148,6 +171,8 @@ if len(bm) == 2:
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drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
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elif buildEnv['TARGET_ISA'] == 'x86':
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drive_sys = makeX86System(drive_mem_mode, np, bm[1])
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elif buildEnv['TARGET_ISA'] == 'arm':
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drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1])
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drive_sys.cpu = DriveCPUClass(cpu_id=0)
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drive_sys.cpu.connectMemPorts(drive_sys.membus)
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if options.fastmem:
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