CPU: Check that the interrupt controller is created when needed

This patch adds a creation-time check to the CPU to ensure that the
interrupt controller is created for the cases where it is needed,
i.e. if the CPU is not being switched in later and not a checker CPU.

The patch also adds the "createInterruptController" call to a number
of the regression scripts.
This commit is contained in:
Andreas Hansson 2012-03-02 09:21:48 -05:00
parent c0b9f324bf
commit 32eae8094d
31 changed files with 81 additions and 7 deletions

View file

@ -118,7 +118,7 @@ CPUProgressEvent::description() const
return "CPU Progress"; return "CPU Progress";
} }
BaseCPU::BaseCPU(Params *p) BaseCPU::BaseCPU(Params *p, bool is_checker)
: MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id), : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
_instMasterId(p->system->getMasterId(name() + ".inst")), _instMasterId(p->system->getMasterId(name() + ".inst")),
_dataMasterId(p->system->getMasterId(name() + ".data")), _dataMasterId(p->system->getMasterId(name() + ".data")),
@ -219,10 +219,17 @@ BaseCPU::BaseCPU(Params *p)
schedule(event, p->function_trace_start); schedule(event, p->function_trace_start);
} }
} }
// Check if CPU model has interrupts connected. The CheckerCPU
// cannot take interrupts directly for example. // The interrupts should always be present unless this CPU is
if (interrupts) // switched in later or in case it is a checker CPU
if (!params()->defer_registration && !is_checker) {
if (interrupts) {
interrupts->setCPU(this); interrupts->setCPU(this);
} else {
fatal("CPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name());
}
}
if (FullSystem) { if (FullSystem) {
profileEvent = NULL; profileEvent = NULL;

View file

@ -302,7 +302,7 @@ class BaseCPU : public MemObject
typedef BaseCPUParams Params; typedef BaseCPUParams Params;
const Params *params() const const Params *params() const
{ return reinterpret_cast<const Params *>(_params); } { return reinterpret_cast<const Params *>(_params); }
BaseCPU(Params *params); BaseCPU(Params *params, bool is_checker = false);
virtual ~BaseCPU(); virtual ~BaseCPU();
virtual void init(); virtual void init();

View file

@ -64,7 +64,7 @@ CheckerCPU::init()
} }
CheckerCPU::CheckerCPU(Params *p) CheckerCPU::CheckerCPU(Params *p)
: BaseCPU(p), thread(NULL), tc(NULL) : BaseCPU(p, true), thread(NULL), tc(NULL)
{ {
memReq = NULL; memReq = NULL;
curStaticInst = NULL; curStaticInst = NULL;

View file

@ -387,6 +387,12 @@ InOrderCPU::InOrderCPU(Params *params)
} }
// InOrderCPU always requires an interrupt controller.
if (!params->defer_registration && !interrupts) {
fatal("InOrderCPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name());
}
dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0); dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
dummyReqInst->setSquashed(); dummyReqInst->setSquashed();
dummyReqInst->resetInstCount(); dummyReqInst->resetInstCount();

View file

@ -460,6 +460,12 @@ FullO3CPU<Impl>::FullO3CPU(DerivO3CPUParams *params)
this->threadContexts.push_back(tc); this->threadContexts.push_back(tc);
} }
// FullO3CPU always requires an interrupt controller.
if (!params->defer_registration && !interrupts) {
fatal("FullO3CPU %s has no interrupt controller.\n"
"Ensure createInterruptController() is called.\n", name());
}
for (ThreadID tid = 0; tid < this->numThreads; tid++) for (ThreadID tid = 0; tid < this->numThreads; tid++)
this->thread[tid]->setFuncExeInst(0); this->thread[tid]->setFuncExeInst(0);

View file

@ -52,6 +52,8 @@ system = System(cpu = cpu,
membus = Bus()) membus = Bus())
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system) root = Root(full_system = False, system = system)

View file

@ -40,6 +40,8 @@ ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores)
system = System(cpu = cpus, physmem = ruby_memory, membus = Bus()) system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
for cpu in cpus: for cpu in cpus:
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -71,6 +71,8 @@ system.l2c.mem_side = system.membus.slave
for cpu in cpus: for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -41,6 +41,8 @@ system = System(cpu = cpu,
physmem = ruby_memory, physmem = ruby_memory,
membus = Bus()) membus = Bus())
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)
# Connect the system port for loading of binaries etc # Connect the system port for loading of binaries etc

View file

@ -52,6 +52,8 @@ system = System(cpu = cpu,
membus = Bus()) membus = Bus())
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)
root = Root(full_system = False, system = system) root = Root(full_system = False, system = system)

View file

@ -104,6 +104,8 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4), L1(size = '32kB', assoc = 4),
PageTableWalkerCache(), PageTableWalkerCache(),
PageTableWalkerCache()) PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -106,6 +106,8 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4), L1(size = '32kB', assoc = 4),
PageTableWalkerCache(), PageTableWalkerCache(),
PageTableWalkerCache()) PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -106,6 +106,8 @@ cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4), L1(size = '32kB', assoc = 4),
PageTableWalkerCache(), PageTableWalkerCache(),
PageTableWalkerCache()) PageTableWalkerCache())
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -86,6 +86,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -70,6 +70,8 @@ system.l2c.mem_side = system.membus.slave
for cpu in cpus: for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -34,6 +34,8 @@ system = System(cpu = AtomicSimpleCPU(cpu_id=0),
membus = Bus()) membus = Bus())
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller
system.cpu.createInterruptController()
system.cpu.connectAllPorts(system.membus) system.cpu.connectAllPorts(system.membus)
system.cpu.clock = '2GHz' system.cpu.clock = '2GHz'

View file

@ -70,6 +70,8 @@ system.l2c.mem_side = system.membus.slave
for cpu in cpus: for cpu in cpus:
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -75,6 +75,9 @@ Ruby.create_system(options, system)
assert(len(system.ruby._cpu_ruby_ports) == 1) assert(len(system.ruby._cpu_ruby_ports) == 1)
# create the interrupt controller
cpu.createInterruptController()
# #
# Tie the cpu cache ports to the ruby cpu ports and # Tie the cpu cache ports to the ruby cpu ports and
# physmem, respectively # physmem, respectively

View file

@ -48,6 +48,8 @@ system = System(cpu = cpu,
membus = Bus()) membus = Bus())
system.system_port = system.membus.slave system.system_port = system.membus.slave
system.physmem.port = system.membus.master system.physmem.port = system.membus.master
# create the interrupt controller
cpu.createInterruptController()
cpu.connectAllPorts(system.membus) cpu.connectAllPorts(system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -90,6 +90,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -89,6 +89,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -87,6 +87,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -88,6 +88,8 @@ system.l2c.mem_side = system.membus.slave
for c in cpus: for c in cpus:
c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
c.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
c.connectAllPorts(system.toL2Bus, system.membus) c.connectAllPorts(system.toL2Bus, system.membus)
c.clock = '2GHz' c.clock = '2GHz'

View file

@ -89,6 +89,8 @@ system.l2c.mem_side = system.membus.slave
#connect up the cpu and l1s #connect up the cpu and l1s
cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1), cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
L1(size = '32kB', assoc = 4)) L1(size = '32kB', assoc = 4))
# create the interrupt controller
cpu.createInterruptController()
# connect cpu level-1 caches to shared level-2 cache # connect cpu level-1 caches to shared level-2 cache
cpu.connectAllPorts(system.toL2Bus, system.membus) cpu.connectAllPorts(system.toL2Bus, system.membus)
cpu.clock = '2GHz' cpu.clock = '2GHz'

View file

@ -35,6 +35,8 @@ from Benchmarks import *
test_sys = makeLinuxAlphaSystem('atomic', test_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-stream-client.rcS')) SysConfig('netperf-stream-client.rcS'))
test_sys.cpu = AtomicSimpleCPU(cpu_id=0) test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
test_sys.cpu.createInterruptController()
test_sys.cpu.connectAllPorts(test_sys.membus) test_sys.cpu.connectAllPorts(test_sys.membus)
# In contrast to the other (one-system) Tsunami configurations we do # In contrast to the other (one-system) Tsunami configurations we do
# not have an IO cache but instead rely on an IO bridge for accesses # not have an IO cache but instead rely on an IO bridge for accesses
@ -47,6 +49,8 @@ test_sys.iobridge.master = test_sys.membus.slave
drive_sys = makeLinuxAlphaSystem('atomic', drive_sys = makeLinuxAlphaSystem('atomic',
SysConfig('netperf-server.rcS')) SysConfig('netperf-server.rcS'))
drive_sys.cpu = AtomicSimpleCPU(cpu_id=0) drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
# create the interrupt controller
drive_sys.cpu.createInterruptController()
drive_sys.cpu.connectAllPorts(drive_sys.membus) drive_sys.cpu.connectAllPorts(drive_sys.membus)
drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
ranges = [AddrRange(0, '8GB')]) ranges = [AddrRange(0, '8GB')])