Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics of the ISA in the CPU.
This commit is contained in:
parent
3e2cad8370
commit
32daf6fc3f
46 changed files with 1068 additions and 480 deletions
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@ -46,6 +46,7 @@ isa_switch_hdrs = Split('''
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arguments.hh
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faults.hh
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interrupts.hh
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isa.hh
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isa_traits.hh
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kernel_stats.hh
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locked_mem.hh
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@ -37,6 +37,7 @@ if env['TARGET_ISA'] == 'alpha':
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Source('floatregfile.cc')
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Source('intregfile.cc')
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Source('ipr.cc')
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Source('isa.cc')
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Source('miscregfile.cc')
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Source('pagetable.cc')
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Source('regfile.cc')
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79
src/arch/alpha/isa.cc
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79
src/arch/alpha/isa.cc
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@ -0,0 +1,79 @@
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/alpha/isa.hh"
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#include "cpu/thread_context.hh"
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namespace AlphaISA
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{
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void
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ISA::clear()
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{
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miscRegFile.clear();
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
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{
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miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
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}
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void
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ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
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{
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miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
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}
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void
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ISA::serialize(std::ostream &os)
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{
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miscRegFile.serialize(os);
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}
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void
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ISA::unserialize(Checkpoint *cp, const std::string §ion)
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{
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miscRegFile.unserialize(cp, section);
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}
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}
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101
src/arch/alpha/isa.hh
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101
src/arch/alpha/isa.hh
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@ -0,0 +1,101 @@
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met: redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer;
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* redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution;
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* neither the name of the copyright holders nor the names of its
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* contributors may be used to endorse or promote products derived from
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* this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ALPHA_ISA_HH__
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#define __ARCH_ALPHA_ISA_HH__
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#include "arch/alpha/miscregfile.hh"
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#include "arch/alpha/types.hh"
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class Checkpoint;
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class EventManager;
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namespace AlphaISA
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{
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class ISA
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{
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protected:
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MiscRegFile miscRegFile;
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public:
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void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
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{
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miscRegFile.expandForMultithreading(num_threads, num_vpes);
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}
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void reset(std::string core_name, ThreadID num_threads,
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unsigned num_vpes, BaseCPU *_cpu)
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{
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miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
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}
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int instAsid()
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{
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return miscRegFile.getInstAsid();
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}
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int dataAsid()
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{
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return miscRegFile.getDataAsid();
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}
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void clear();
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MiscReg readMiscRegNoEffect(int miscReg);
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MiscReg readMiscReg(int miscReg, ThreadContext *tc);
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void setMiscRegNoEffect(int miscReg, const MiscReg val);
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void setMiscReg(int miscReg, const MiscReg val,
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ThreadContext *tc);
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int
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flattenIntIndex(int reg)
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{
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return reg;
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}
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int
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flattenFloatIndex(int reg)
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{
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return reg;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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ISA()
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{
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clear();
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}
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};
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}
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#endif
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@ -55,6 +55,7 @@ output header {{
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output decoder {{
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#include <cmath>
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#include "arch/alpha/miscregfile.hh"
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#include "base/cprintf.hh"
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#include "base/fenv.hh"
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#include "base/loader/symtab.hh"
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@ -71,6 +72,7 @@ output exec {{
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#include "base/cp_annotate.hh"
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#include "sim/pseudo_inst.hh"
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#include "arch/alpha/ipr.hh"
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#include "arch/alpha/miscregfile.hh"
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#include "base/fenv.hh"
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#include "config/ss_compatible_fp.hh"
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#include "cpu/base.hh"
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@ -31,6 +31,7 @@
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*/
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#include "arch/alpha/regfile.hh"
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#include "arch/alpha/miscregfile.hh"
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#include "cpu/thread_context.hh"
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using namespace std;
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@ -42,7 +43,6 @@ RegFile::serialize(EventManager *em, ostream &os)
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{
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intRegFile.serialize(os);
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floatRegFile.serialize(os);
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miscRegFile.serialize(os);
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SERIALIZE_SCALAR(pc);
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SERIALIZE_SCALAR(npc);
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#if FULL_SYSTEM
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@ -55,7 +55,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
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{
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intRegFile.unserialize(cp, section);
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floatRegFile.unserialize(cp, section);
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miscRegFile.unserialize(cp, section);
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UNSERIALIZE_SCALAR(pc);
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UNSERIALIZE_SCALAR(npc);
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#if FULL_SYSTEM
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@ -93,23 +93,10 @@ class RegFile {
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protected:
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IntRegFile intRegFile; // (signed) integer register file
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FloatRegFile floatRegFile; // floating point register file
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MiscRegFile miscRegFile; // control register file
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public:
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#if FULL_SYSTEM
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int intrflag; // interrupt flag
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int
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instAsid()
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{
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return miscRegFile.getInstAsid();
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}
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int
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dataAsid()
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{
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return miscRegFile.getDataAsid();
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}
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#endif // FULL_SYSTEM
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void
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{
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intRegFile.clear();
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floatRegFile.clear();
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miscRegFile.clear();
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}
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MiscReg
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readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect(miscReg);
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}
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MiscReg
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readMiscReg(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readReg(miscReg, tc);
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}
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void
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setMiscRegNoEffect(int miscReg, const MiscReg &val)
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{
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miscRegFile.setRegNoEffect(miscReg, val);
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}
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void
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setMiscReg(int miscReg, const MiscReg &val, ThreadContext *tc)
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{
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miscRegFile.setReg(miscReg, val, tc);
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}
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FloatReg
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const std::string §ion);
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};
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static inline int
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flattenIntIndex(ThreadContext * tc, int reg)
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{
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return reg;
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}
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static inline int
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flattenFloatIndex(ThreadContext * tc, int reg)
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{
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return reg;
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}
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void copyRegs(ThreadContext *src, ThreadContext *dest);
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void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
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@ -39,6 +39,7 @@ if env['TARGET_ISA'] == 'arm':
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Source('insts/mem.cc')
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Source('insts/pred_inst.cc')
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Source('insts/static_inst.cc')
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Source('isa.cc')
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Source('pagetable.cc')
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Source('regfile/regfile.cc')
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Source('tlb.cc')
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79
src/arch/arm/isa.cc
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79
src/arch/arm/isa.cc
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Authors: Gabe Black
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*/
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#include "arch/arm/isa.hh"
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#include "cpu/thread_context.hh"
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namespace ArmISA
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{
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void
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ISA::clear()
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{
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miscRegFile.clear();
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}
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MiscReg
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ISA::readMiscRegNoEffect(int miscReg)
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{
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return miscRegFile.readRegNoEffect(miscReg);
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}
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MiscReg
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ISA::readMiscReg(int miscReg, ThreadContext *tc)
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{
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return miscRegFile.readReg(miscReg, tc);
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}
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void
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ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
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{
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miscRegFile.setRegNoEffect(miscReg, val);
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}
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void
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ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
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{
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miscRegFile.setReg(miscReg, val, tc);
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}
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void
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ISA::serialize(std::ostream &os)
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{
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//miscRegFile.serialize(os);
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}
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void
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ISA::unserialize(Checkpoint *cp, const std::string §ion)
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{
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//miscRegFile.unserialize(cp, section);
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}
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}
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79
src/arch/arm/isa.hh
Normal file
79
src/arch/arm/isa.hh
Normal file
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/*
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* Copyright (c) 2009 The Regents of The University of Michigan
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||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
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*
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* Authors: Gabe Black
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*/
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#ifndef __ARCH_ARM_ISA_HH__
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#define __ARCH_MRM_ISA_HH__
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#include "arch/arm/regfile/misc_regfile.hh"
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#include "arch/arm/types.hh"
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class Checkpoint;
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class EventManager;
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namespace ArmISA
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{
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class ISA
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{
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protected:
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MiscRegFile miscRegFile;
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public:
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void clear();
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MiscReg readMiscRegNoEffect(int miscReg);
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MiscReg readMiscReg(int miscReg, ThreadContext *tc);
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void setMiscRegNoEffect(int miscReg, const MiscReg val);
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void setMiscReg(int miscReg, const MiscReg val,
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ThreadContext *tc);
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int
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flattenIntIndex(int reg)
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{
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return reg;
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}
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int
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flattenFloatIndex(int reg)
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{
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return reg;
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}
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void serialize(std::ostream &os);
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void unserialize(Checkpoint *cp, const std::string §ion);
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ISA()
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{
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clear();
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}
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};
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}
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#endif
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@ -31,6 +31,7 @@
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#ifndef __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
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#define __ARCH_ARM_REGFILE_MISC_REGFILE_HH__
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#include "arch/arm/isa_traits.hh"
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#include "arch/arm/types.hh"
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#include "sim/faults.hh"
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|
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@ -59,11 +59,6 @@ RegFile::serialize(EventManager *em, ostream &os)
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{
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intRegFile.serialize(os);
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//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
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//SERIALZE_ARRAY(miscRegFile);
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//SERIALIZE_SCALAR(miscRegs.fpcr);
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//SERIALIZE_SCALAR(miscRegs.lock_flag);
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//SERIALIZE_SCALAR(miscRegs.lock_addr);
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//SERIALIZE_SCALAR(pc);
|
||||
SERIALIZE_SCALAR(npc);
|
||||
SERIALIZE_SCALAR(nnpc);
|
||||
}
|
||||
|
@ -73,14 +68,8 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
|||
{
|
||||
intRegFile.unserialize(cp, section);
|
||||
//UNSERIALIZE_ARRAY(floatRegFile);
|
||||
//UNSERIALZE_ARRAY(miscRegFile);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
|
||||
//UNSERIALIZE_SCALAR(pc);
|
||||
UNSERIALIZE_SCALAR(npc);
|
||||
UNSERIALIZE_SCALAR(nnpc);
|
||||
|
||||
}
|
||||
|
||||
} // namespace ArmISA
|
||||
|
|
|
@ -48,7 +48,6 @@ namespace ArmISA
|
|||
protected:
|
||||
IntRegFile intRegFile; // (signed) integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
|
||||
public:
|
||||
|
||||
|
@ -56,28 +55,6 @@ namespace ArmISA
|
|||
{
|
||||
intRegFile.clear();
|
||||
floatRegFile.clear();
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect(miscReg);
|
||||
}
|
||||
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg(miscReg, tc);
|
||||
}
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg &val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect(miscReg, val);
|
||||
}
|
||||
|
||||
void setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc)
|
||||
{
|
||||
miscRegFile.setReg(miscReg, val, tc);
|
||||
}
|
||||
|
||||
FloatRegVal readFloatReg(int floatReg)
|
||||
|
@ -171,22 +148,8 @@ namespace ArmISA
|
|||
void serialize(EventManager *em, std::ostream &os);
|
||||
void unserialize(EventManager *em, Checkpoint *cp,
|
||||
const std::string §ion);
|
||||
|
||||
void changeContext(RegContextParam param, RegContextVal val)
|
||||
{
|
||||
}
|
||||
};
|
||||
|
||||
static inline int flattenIntIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
static inline int flattenFloatIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
||||
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
|
|
@ -34,6 +34,7 @@ Import('*')
|
|||
|
||||
if env['TARGET_ISA'] == 'mips':
|
||||
Source('faults.cc')
|
||||
Source('isa.cc')
|
||||
Source('regfile/int_regfile.cc')
|
||||
Source('regfile/float_regfile.cc')
|
||||
Source('regfile/misc_regfile.cc')
|
||||
|
|
80
src/arch/mips/isa.cc
Normal file
80
src/arch/mips/isa.cc
Normal file
|
@ -0,0 +1,80 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#include "arch/mips/isa.hh"
|
||||
#include "arch/mips/regfile/misc_regfile.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
|
||||
namespace MipsISA
|
||||
{
|
||||
|
||||
void
|
||||
ISA::clear()
|
||||
{
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect(miscReg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg(miscReg, tc);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect(miscReg, val);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
|
||||
{
|
||||
miscRegFile.setReg(miscReg, val, tc);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::serialize(std::ostream &os)
|
||||
{
|
||||
//miscRegFile.serialize(os);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::unserialize(Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
//miscRegFile.unserialize(cp, section);
|
||||
}
|
||||
|
||||
}
|
101
src/arch/mips/isa.hh
Normal file
101
src/arch/mips/isa.hh
Normal file
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_MIPS_ISA_HH__
|
||||
#define __ARCH_MIPS_ISA_HH__
|
||||
|
||||
#include "arch/mips/regfile/misc_regfile.hh"
|
||||
#include "arch/mips/types.hh"
|
||||
|
||||
class Checkpoint;
|
||||
class EventManager;
|
||||
|
||||
namespace MipsISA
|
||||
{
|
||||
class ISA
|
||||
{
|
||||
protected:
|
||||
MiscRegFile miscRegFile;
|
||||
|
||||
public:
|
||||
|
||||
void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
|
||||
{
|
||||
miscRegFile.expandForMultithreading(num_threads, num_vpes);
|
||||
}
|
||||
|
||||
void reset(std::string core_name, ThreadID num_threads,
|
||||
unsigned num_vpes, BaseCPU *_cpu)
|
||||
{
|
||||
miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
|
||||
}
|
||||
|
||||
int instAsid()
|
||||
{
|
||||
return miscRegFile.getInstAsid();
|
||||
}
|
||||
|
||||
int dataAsid()
|
||||
{
|
||||
return miscRegFile.getDataAsid();
|
||||
}
|
||||
|
||||
void clear();
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg);
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg val);
|
||||
void setMiscReg(int miscReg, const MiscReg val,
|
||||
ThreadContext *tc);
|
||||
|
||||
int
|
||||
flattenIntIndex(int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
int
|
||||
flattenFloatIndex(int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
void serialize(std::ostream &os);
|
||||
void unserialize(Checkpoint *cp, const std::string §ion);
|
||||
|
||||
ISA()
|
||||
{
|
||||
clear();
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
|
@ -193,11 +193,6 @@ RegFile::unserialize(Checkpoint *cp, const std::string §ion)
|
|||
|
||||
}
|
||||
|
||||
static inline int flattenIntIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
void
|
||||
MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
||||
{
|
||||
|
|
|
@ -42,7 +42,6 @@ RegFile::clear()
|
|||
{
|
||||
intRegFile.clear();
|
||||
floatRegFile.clear();
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
void
|
||||
|
@ -51,7 +50,6 @@ RegFile::reset(std::string core_name, ThreadID num_threads, unsigned num_vpes,
|
|||
{
|
||||
bzero(&intRegFile, sizeof(intRegFile));
|
||||
bzero(&floatRegFile, sizeof(floatRegFile));
|
||||
miscRegFile.reset(core_name, num_threads, num_vpes, _cpu);
|
||||
}
|
||||
|
||||
IntReg
|
||||
|
@ -66,31 +64,6 @@ RegFile::setIntReg(int intReg, const IntReg &val)
|
|||
return intRegFile.setReg(intReg, val);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
RegFile::readMiscRegNoEffect(int miscReg, ThreadID tid)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect(miscReg, tid);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
RegFile::readMiscReg(int miscReg, ThreadContext *tc, ThreadID tid)
|
||||
{
|
||||
return miscRegFile.readReg(miscReg, tc, tid);
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val, ThreadID tid)
|
||||
{
|
||||
miscRegFile.setRegNoEffect(miscReg, val, tid);
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext *tc, ThreadID tid)
|
||||
{
|
||||
miscRegFile.setReg(miscReg, val, tc, tid);
|
||||
}
|
||||
|
||||
FloatRegVal
|
||||
RegFile::readFloatReg(int floatReg)
|
||||
{
|
||||
|
@ -144,17 +117,6 @@ RegFile::setShadowSet(int css){
|
|||
intRegFile.setShadowSet(css);
|
||||
}
|
||||
|
||||
int
|
||||
RegFile::instAsid()
|
||||
{
|
||||
return miscRegFile.getInstAsid();
|
||||
}
|
||||
|
||||
int
|
||||
RegFile::dataAsid()
|
||||
{
|
||||
return miscRegFile.getDataAsid();
|
||||
}
|
||||
|
||||
Addr
|
||||
RegFile::readPC()
|
||||
|
@ -197,10 +159,6 @@ RegFile::serialize(EventManager *em, std::ostream &os)
|
|||
{
|
||||
intRegFile.serialize(os);
|
||||
//SERIALIZE_ARRAY(floatRegFile, NumFloatRegs);
|
||||
//SERIALZE_ARRAY(miscRegFile);
|
||||
//SERIALIZE_SCALAR(miscRegs.fpcr);
|
||||
//SERIALIZE_SCALAR(miscRegs.lock_flag);
|
||||
//SERIALIZE_SCALAR(miscRegs.lock_addr);
|
||||
SERIALIZE_SCALAR(pc);
|
||||
SERIALIZE_SCALAR(npc);
|
||||
SERIALIZE_SCALAR(nnpc);
|
||||
|
@ -212,14 +170,9 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp,
|
|||
{
|
||||
intRegFile.unserialize(cp, section);
|
||||
//UNSERIALIZE_ARRAY(floatRegFile);
|
||||
//UNSERIALZE_ARRAY(miscRegFile);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.fpcr);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.lock_flag);
|
||||
//UNSERIALIZE_SCALAR(miscRegs.lock_addr);
|
||||
UNSERIALIZE_SCALAR(pc);
|
||||
UNSERIALIZE_SCALAR(npc);
|
||||
UNSERIALIZE_SCALAR(nnpc);
|
||||
|
||||
}
|
||||
|
||||
} // namespace MipsISA
|
||||
|
|
|
@ -37,7 +37,6 @@
|
|||
//#include "arch/mips/mt.hh"
|
||||
#include "arch/mips/regfile/int_regfile.hh"
|
||||
#include "arch/mips/regfile/float_regfile.hh"
|
||||
#include "arch/mips/regfile/misc_regfile.hh"
|
||||
//#include "cpu/base.hh"
|
||||
#include "sim/faults.hh"
|
||||
|
||||
|
@ -57,26 +56,16 @@ namespace MipsISA
|
|||
|
||||
IntRegFile intRegFile; // (signed) integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
|
||||
public:
|
||||
void clear();
|
||||
void reset(std::string core_name, ThreadID num_threads,
|
||||
unsigned num_vpes, BaseCPU *_cpu);
|
||||
MiscRegFile *getMiscRegFilePtr();
|
||||
|
||||
IntReg readIntReg(int intReg);
|
||||
Fault setIntReg(int intReg, const IntReg &val);
|
||||
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg, ThreadID tid = 0);
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc,
|
||||
ThreadID tid = 0);
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg &val,
|
||||
ThreadID tid = 0);
|
||||
void setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext *tc, ThreadID tid = 0);
|
||||
|
||||
FloatRegVal readFloatReg(int floatReg);
|
||||
FloatRegVal readFloatReg(int floatReg, int width);
|
||||
FloatRegBits readFloatRegBits(int floatReg);
|
||||
|
@ -89,9 +78,6 @@ namespace MipsISA
|
|||
|
||||
void setShadowSet(int css);
|
||||
|
||||
int instAsid();
|
||||
int dataAsid();
|
||||
|
||||
public:
|
||||
Addr readPC();
|
||||
void setPC(Addr val);
|
||||
|
|
|
@ -98,17 +98,6 @@ namespace MipsISA {
|
|||
//
|
||||
// Register File Utility Functions
|
||||
//
|
||||
static inline int flattenFloatIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
static inline int flattenIntIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
// Implement Shadow Sets Stuff Here;
|
||||
return reg;
|
||||
}
|
||||
|
||||
static inline MachInst makeRegisterCopy(int dest, int src) {
|
||||
panic("makeRegisterCopy not implemented");
|
||||
return 0;
|
||||
|
|
|
@ -36,6 +36,7 @@ if env['TARGET_ISA'] == 'sparc':
|
|||
Source('faults.cc')
|
||||
Source('floatregfile.cc')
|
||||
Source('intregfile.cc')
|
||||
Source('isa.cc')
|
||||
Source('miscregfile.cc')
|
||||
Source('pagetable.cc')
|
||||
Source('regfile.cc')
|
||||
|
|
147
src/arch/sparc/isa.cc
Normal file
147
src/arch/sparc/isa.cc
Normal file
|
@ -0,0 +1,147 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#include "arch/sparc/isa.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
|
||||
namespace SparcISA
|
||||
{
|
||||
|
||||
void
|
||||
ISA::clear()
|
||||
{
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
|
||||
{
|
||||
miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
|
||||
}
|
||||
|
||||
int
|
||||
ISA::flattenIntIndex(int reg)
|
||||
{
|
||||
int gl = miscRegFile.readRegNoEffect(MISCREG_GL);
|
||||
int cwp = miscRegFile.readRegNoEffect(MISCREG_CWP);
|
||||
//DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
|
||||
int newReg;
|
||||
//The total number of global registers
|
||||
int numGlobals = (MaxGL + 1) * 8;
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else if(reg < NumIntArchRegs)
|
||||
{
|
||||
//Regular windowed register
|
||||
//Put it in the window pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
else if(reg < NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
//Microcode register
|
||||
//Displace from the end of the regular registers
|
||||
newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
|
||||
}
|
||||
else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
reg -= (NumIntArchRegs + NumMicroIntRegs);
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register from the next window
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Windowed register from the previous window
|
||||
//Put it in the window before the one pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
}
|
||||
else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register from the previous window
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Windowed register from the next window
|
||||
//Put it in the window after the one pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
}
|
||||
else
|
||||
panic("Tried to flatten invalid register index %d!\n", reg);
|
||||
DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
|
||||
return newReg;
|
||||
}
|
||||
|
||||
void
|
||||
ISA::serialize(EventManager *em, std::ostream &os)
|
||||
{
|
||||
miscRegFile.serialize(em, os);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
miscRegFile.unserialize(em, cp, section);
|
||||
}
|
||||
|
||||
}
|
87
src/arch/sparc/isa.hh
Normal file
87
src/arch/sparc/isa.hh
Normal file
|
@ -0,0 +1,87 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_SPARC_ISA_HH__
|
||||
#define __ARCH_SPARC_ISA_HH__
|
||||
|
||||
#include "arch/sparc/miscregfile.hh"
|
||||
#include "arch/sparc/types.hh"
|
||||
|
||||
class Checkpoint;
|
||||
class EventManager;
|
||||
|
||||
namespace SparcISA
|
||||
{
|
||||
class ISA
|
||||
{
|
||||
protected:
|
||||
MiscRegFile miscRegFile;
|
||||
|
||||
public:
|
||||
|
||||
int instAsid()
|
||||
{
|
||||
return miscRegFile.getInstAsid();
|
||||
}
|
||||
|
||||
int dataAsid()
|
||||
{
|
||||
return miscRegFile.getDataAsid();
|
||||
}
|
||||
|
||||
void clear();
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg);
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg val);
|
||||
void setMiscReg(int miscReg, const MiscReg val,
|
||||
ThreadContext *tc);
|
||||
|
||||
int flattenIntIndex(int reg);
|
||||
|
||||
int
|
||||
flattenFloatIndex(int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
void serialize(EventManager *em, std::ostream &os);
|
||||
void unserialize(EventManager *em, Checkpoint *cp,
|
||||
const std::string §ion);
|
||||
|
||||
ISA()
|
||||
{
|
||||
clear();
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
|
@ -72,28 +72,6 @@ void RegFile::clear()
|
|||
{
|
||||
floatRegFile.clear();
|
||||
intRegFile.clear();
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg RegFile::readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect(miscReg);
|
||||
}
|
||||
|
||||
MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg(miscReg, tc);
|
||||
}
|
||||
|
||||
void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect(miscReg, val);
|
||||
}
|
||||
|
||||
void RegFile::setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc)
|
||||
{
|
||||
miscRegFile.setReg(miscReg, val, tc);
|
||||
}
|
||||
|
||||
FloatReg RegFile::readFloatReg(int floatReg, int width)
|
||||
|
@ -151,80 +129,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
|
|||
intRegFile.setReg(intReg, val);
|
||||
}
|
||||
|
||||
int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
int gl = tc->readMiscRegNoEffect(MISCREG_GL);
|
||||
int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
|
||||
//DPRINTF(RegisterWindows, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
|
||||
int newReg;
|
||||
//The total number of global registers
|
||||
int numGlobals = (MaxGL + 1) * 8;
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else if(reg < NumIntArchRegs)
|
||||
{
|
||||
//Regular windowed register
|
||||
//Put it in the window pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
else if(reg < NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
//Microcode register
|
||||
//Displace from the end of the regular registers
|
||||
newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
|
||||
}
|
||||
else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
reg -= (NumIntArchRegs + NumMicroIntRegs);
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register from the next window
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Windowed register from the previous window
|
||||
//Put it in the window before the one pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
}
|
||||
else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
|
||||
{
|
||||
reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
|
||||
if(reg < 8)
|
||||
{
|
||||
//Global register from the previous window
|
||||
//Put it in the appropriate set of globals
|
||||
newReg = reg + gl * 8;
|
||||
}
|
||||
else
|
||||
{
|
||||
//Windowed register from the next window
|
||||
//Put it in the window after the one pointed to by cwp
|
||||
newReg = numGlobals +
|
||||
((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
|
||||
}
|
||||
}
|
||||
else
|
||||
panic("Tried to flatten invalid register index %d!\n", reg);
|
||||
DPRINTF(RegisterWindows, "Flattened register %d to %d.\n", reg, newReg);
|
||||
return newReg;
|
||||
//return intRegFile.flattenIndex(reg);
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::serialize(EventManager *em, ostream &os)
|
||||
{
|
||||
intRegFile.serialize(os);
|
||||
floatRegFile.serialize(os);
|
||||
miscRegFile.serialize(em, os);
|
||||
SERIALIZE_SCALAR(pc);
|
||||
SERIALIZE_SCALAR(npc);
|
||||
SERIALIZE_SCALAR(nnpc);
|
||||
|
@ -235,7 +144,6 @@ RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
|||
{
|
||||
intRegFile.unserialize(cp, section);
|
||||
floatRegFile.unserialize(cp, section);
|
||||
miscRegFile.unserialize(em, cp, section);
|
||||
UNSERIALIZE_SCALAR(pc);
|
||||
UNSERIALIZE_SCALAR(npc);
|
||||
UNSERIALIZE_SCALAR(nnpc);
|
||||
|
|
|
@ -65,31 +65,11 @@ namespace SparcISA
|
|||
protected:
|
||||
IntRegFile intRegFile; // integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
|
||||
public:
|
||||
|
||||
void clear();
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg);
|
||||
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg &val);
|
||||
|
||||
void setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc);
|
||||
|
||||
int instAsid()
|
||||
{
|
||||
return miscRegFile.getInstAsid();
|
||||
}
|
||||
|
||||
int dataAsid()
|
||||
{
|
||||
return miscRegFile.getDataAsid();
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(int floatReg, int width);
|
||||
|
||||
FloatReg readFloatReg(int floatReg);
|
||||
|
@ -117,14 +97,6 @@ namespace SparcISA
|
|||
public:
|
||||
};
|
||||
|
||||
int flattenIntIndex(ThreadContext * tc, int reg);
|
||||
|
||||
static inline int
|
||||
flattenFloatIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
return reg;
|
||||
}
|
||||
|
||||
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
||||
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
|
|
@ -96,6 +96,7 @@ if env['TARGET_ISA'] == 'x86':
|
|||
Source('insts/microregop.cc')
|
||||
Source('insts/static_inst.cc')
|
||||
Source('intregfile.cc')
|
||||
Source('isa.cc')
|
||||
Source('miscregfile.cc')
|
||||
Source('pagetable.cc')
|
||||
Source('predecoder.cc')
|
||||
|
|
101
src/arch/x86/isa.cc
Normal file
101
src/arch/x86/isa.cc
Normal file
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#include "arch/x86/isa.hh"
|
||||
#include "arch/x86/floatregs.hh"
|
||||
#include "cpu/thread_context.hh"
|
||||
|
||||
namespace X86ISA
|
||||
{
|
||||
|
||||
void
|
||||
ISA::clear()
|
||||
{
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
ISA::readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscRegNoEffect(int miscReg, const MiscReg val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::setMiscReg(int miscReg, const MiscReg val, ThreadContext *tc)
|
||||
{
|
||||
miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
|
||||
}
|
||||
|
||||
int
|
||||
ISA::flattenIntIndex(int reg)
|
||||
{
|
||||
//If we need to fold over the index to match byte semantics, do that.
|
||||
//Otherwise, just strip off any extra bits and pass it through.
|
||||
if (reg & (1 << 6))
|
||||
return (reg & (~(1 << 6) - 0x4));
|
||||
else
|
||||
return (reg & ~(1 << 6));
|
||||
}
|
||||
|
||||
int
|
||||
ISA::flattenFloatIndex(int reg)
|
||||
{
|
||||
if (reg >= NUM_FLOATREGS) {
|
||||
int top = miscRegFile.readRegNoEffect(MISCREG_X87_TOP);
|
||||
reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
|
||||
}
|
||||
return reg;
|
||||
}
|
||||
|
||||
void
|
||||
ISA::serialize(EventManager *em, std::ostream &os)
|
||||
{
|
||||
miscRegFile.serialize(os);
|
||||
}
|
||||
|
||||
void
|
||||
ISA::unserialize(EventManager *em, Checkpoint *cp, const std::string §ion)
|
||||
{
|
||||
miscRegFile.unserialize(cp, section);
|
||||
}
|
||||
|
||||
}
|
78
src/arch/x86/isa.hh
Normal file
78
src/arch/x86/isa.hh
Normal file
|
@ -0,0 +1,78 @@
|
|||
/*
|
||||
* Copyright (c) 2009 The Regents of The University of Michigan
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are
|
||||
* met: redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer;
|
||||
* redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution;
|
||||
* neither the name of the copyright holders nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Authors: Gabe Black
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_X86_ISA_HH__
|
||||
#define __ARCH_X86_ISA_HH__
|
||||
|
||||
#include "arch/x86/miscregfile.hh"
|
||||
#include "arch/x86/types.hh"
|
||||
|
||||
class Checkpoint;
|
||||
class EventManager;
|
||||
|
||||
namespace X86ISA
|
||||
{
|
||||
class ISA
|
||||
{
|
||||
protected:
|
||||
MiscRegFile miscRegFile;
|
||||
|
||||
public:
|
||||
int instAsid()
|
||||
{
|
||||
//XXX This doesn't make sense in x86
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dataAsid()
|
||||
{
|
||||
//XXX This doesn't make sense in x86
|
||||
return 0;
|
||||
}
|
||||
|
||||
void clear();
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg);
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg val);
|
||||
void setMiscReg(int miscReg, const MiscReg val,
|
||||
ThreadContext *tc);
|
||||
|
||||
int flattenIntIndex(int reg);
|
||||
int flattenFloatIndex(int reg);
|
||||
|
||||
void serialize(EventManager *em, std::ostream &os);
|
||||
void unserialize(EventManager *em, Checkpoint *cp,
|
||||
const std::string §ion);
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
|
@ -99,14 +99,10 @@ class Checkpoint;
|
|||
|
||||
namespace X86ISA
|
||||
{
|
||||
//These will have to be updated in the future.
|
||||
const int NumMiscArchRegs = NUM_MISCREGS;
|
||||
const int NumMiscRegs = NUM_MISCREGS;
|
||||
|
||||
class MiscRegFile
|
||||
{
|
||||
protected:
|
||||
MiscReg regVal[NumMiscRegs];
|
||||
MiscReg regVal[NUM_MISCREGS];
|
||||
void updateHandyM5Reg(Efer efer, CR0 cr0,
|
||||
SegAttr csAttr, SegAttr ssAttr, RFLAGS rflags);
|
||||
|
||||
|
|
|
@ -87,6 +87,7 @@
|
|||
*/
|
||||
|
||||
#include "arch/x86/isa_traits.hh"
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/process.hh"
|
||||
#include "arch/x86/segmentregs.hh"
|
||||
#include "arch/x86/types.hh"
|
||||
|
|
|
@ -86,6 +86,7 @@
|
|||
*/
|
||||
|
||||
#include "arch/x86/floatregs.hh"
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/regfile.hh"
|
||||
#include "base/trace.hh"
|
||||
#include "sim/serialize.hh"
|
||||
|
@ -130,28 +131,6 @@ void RegFile::clear()
|
|||
{
|
||||
floatRegFile.clear();
|
||||
intRegFile.clear();
|
||||
miscRegFile.clear();
|
||||
}
|
||||
|
||||
MiscReg RegFile::readMiscRegNoEffect(int miscReg)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect((MiscRegIndex)miscReg);
|
||||
}
|
||||
|
||||
MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
|
||||
{
|
||||
return miscRegFile.readReg((MiscRegIndex)miscReg, tc);
|
||||
}
|
||||
|
||||
void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
|
||||
{
|
||||
miscRegFile.setRegNoEffect((MiscRegIndex)miscReg, val);
|
||||
}
|
||||
|
||||
void RegFile::setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc)
|
||||
{
|
||||
miscRegFile.setReg((MiscRegIndex)miscReg, val, tc);
|
||||
}
|
||||
|
||||
FloatReg RegFile::readFloatReg(int floatReg, int width)
|
||||
|
@ -209,50 +188,11 @@ void RegFile::setIntReg(int intReg, const IntReg &val)
|
|||
intRegFile.setReg(intReg, val);
|
||||
}
|
||||
|
||||
int X86ISA::flattenIntIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
//If we need to fold over the index to match byte semantics, do that.
|
||||
//Otherwise, just strip off any extra bits and pass it through.
|
||||
if (reg & (1 << 6))
|
||||
return (reg & (~(1 << 6) - 0x4));
|
||||
else
|
||||
return (reg & ~(1 << 6));
|
||||
}
|
||||
|
||||
int X86ISA::flattenFloatIndex(ThreadContext * tc, int reg)
|
||||
{
|
||||
if (reg >= NUM_FLOATREGS) {
|
||||
int top = tc->readMiscRegNoEffect(MISCREG_X87_TOP);
|
||||
reg = FLOATREG_STACK(reg - NUM_FLOATREGS, top);
|
||||
}
|
||||
return reg;
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::serialize(EventManager *em, std::ostream &os)
|
||||
X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
|
||||
{
|
||||
intRegFile.serialize(os);
|
||||
floatRegFile.serialize(os);
|
||||
miscRegFile.serialize(os);
|
||||
SERIALIZE_SCALAR(rip);
|
||||
SERIALIZE_SCALAR(nextRip);
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
||||
{
|
||||
intRegFile.unserialize(cp, section);
|
||||
floatRegFile.unserialize(cp, section);
|
||||
miscRegFile.unserialize(cp, section);
|
||||
UNSERIALIZE_SCALAR(rip);
|
||||
UNSERIALIZE_SCALAR(nextRip);
|
||||
}
|
||||
|
||||
void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
|
||||
{
|
||||
//panic("copyMiscRegs not implemented for x86!\n");
|
||||
warn("copyMiscRegs is naively implemented for x86\n");
|
||||
for (int i = 0; i < X86ISA::NumMiscRegs; ++i) {
|
||||
for (int i = 0; i < NUM_MISCREGS; ++i) {
|
||||
if ( ( i != MISCREG_CR1 &&
|
||||
!(i > MISCREG_CR4 && i < MISCREG_CR8) &&
|
||||
!(i > MISCREG_CR8 && i <= MISCREG_CR15) ) == false) {
|
||||
|
@ -260,10 +200,10 @@ void X86ISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
|
|||
}
|
||||
dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
||||
void
|
||||
X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
||||
{
|
||||
panic("copyRegs not implemented for x86!\n");
|
||||
//copy int regs
|
||||
|
@ -273,3 +213,17 @@ void X86ISA::copyRegs(ThreadContext *src, ThreadContext *dest)
|
|||
dest->setPC(src->readPC());
|
||||
dest->setNextPC(src->readNextPC());
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::serialize(EventManager *em, std::ostream &os)
|
||||
{
|
||||
intRegFile.serialize(os);
|
||||
floatRegFile.serialize(os);
|
||||
}
|
||||
|
||||
void
|
||||
RegFile::unserialize(EventManager *em, Checkpoint *cp, const string §ion)
|
||||
{
|
||||
intRegFile.unserialize(cp, section);
|
||||
floatRegFile.unserialize(cp, section);
|
||||
}
|
||||
|
|
|
@ -62,8 +62,8 @@
|
|||
|
||||
#include "arch/x86/floatregfile.hh"
|
||||
#include "arch/x86/intregfile.hh"
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/isa_traits.hh"
|
||||
#include "arch/x86/miscregfile.hh"
|
||||
#include "arch/x86/types.hh"
|
||||
#include "base/types.hh"
|
||||
|
||||
|
@ -72,6 +72,9 @@ class EventManager;
|
|||
|
||||
namespace X86ISA
|
||||
{
|
||||
const int NumMiscArchRegs = NUM_MISCREGS;
|
||||
const int NumMiscRegs = NUM_MISCREGS;
|
||||
|
||||
class RegFile
|
||||
{
|
||||
protected:
|
||||
|
@ -91,33 +94,11 @@ namespace X86ISA
|
|||
protected:
|
||||
IntRegFile intRegFile; // integer register file
|
||||
FloatRegFile floatRegFile; // floating point register file
|
||||
MiscRegFile miscRegFile; // control register file
|
||||
|
||||
public:
|
||||
|
||||
void clear();
|
||||
|
||||
MiscReg readMiscRegNoEffect(int miscReg);
|
||||
|
||||
MiscReg readMiscReg(int miscReg, ThreadContext *tc);
|
||||
|
||||
void setMiscRegNoEffect(int miscReg, const MiscReg &val);
|
||||
|
||||
void setMiscReg(int miscReg, const MiscReg &val,
|
||||
ThreadContext * tc);
|
||||
|
||||
int instAsid()
|
||||
{
|
||||
//XXX This doesn't make sense in x86
|
||||
return 0;
|
||||
}
|
||||
|
||||
int dataAsid()
|
||||
{
|
||||
//XXX This doesn't make sense in x86
|
||||
return 0;
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(int floatReg, int width);
|
||||
|
||||
FloatReg readFloatReg(int floatReg);
|
||||
|
@ -141,14 +122,8 @@ namespace X86ISA
|
|||
void serialize(EventManager *em, std::ostream &os);
|
||||
void unserialize(EventManager *em, Checkpoint *cp,
|
||||
const std::string §ion);
|
||||
|
||||
public:
|
||||
};
|
||||
|
||||
int flattenIntIndex(ThreadContext * tc, int reg);
|
||||
|
||||
int flattenFloatIndex(ThreadContext * tc, int reg);
|
||||
|
||||
void copyRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
||||
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
|
||||
|
|
|
@ -60,6 +60,7 @@
|
|||
#include "config/full_system.hh"
|
||||
|
||||
#include "arch/x86/insts/microldstop.hh"
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/pagetable.hh"
|
||||
#include "arch/x86/tlb.hh"
|
||||
#include "arch/x86/x86_traits.hh"
|
||||
|
|
|
@ -58,6 +58,7 @@
|
|||
#ifndef __ARCH_X86_UTILITY_HH__
|
||||
#define __ARCH_X86_UTILITY_HH__
|
||||
|
||||
#include "arch/x86/miscregs.hh"
|
||||
#include "arch/x86/types.hh"
|
||||
#include "base/hashmap.hh"
|
||||
#include "base/misc.hh"
|
||||
|
|
|
@ -168,7 +168,6 @@ InOrderCPU::InOrderCPU(Params *params)
|
|||
coreType("default"),
|
||||
_status(Idle),
|
||||
tickEvent(this),
|
||||
miscRegFile(this),
|
||||
timeBuffer(2 , 2),
|
||||
removeInstsThisCycle(false),
|
||||
activityRec(params->name, NumStages, 10, params->activity),
|
||||
|
@ -267,15 +266,11 @@ InOrderCPU::InOrderCPU(Params *params)
|
|||
|
||||
intRegFile[tid].clear();
|
||||
floatRegFile[tid].clear();
|
||||
}
|
||||
isa[tid].clear();
|
||||
|
||||
// Update miscRegFile if necessary
|
||||
if (numThreads > 1) {
|
||||
miscRegFile.expandForMultithreading(numThreads, numVirtProcs);
|
||||
isa[tid].expandForMultithreading(numThreads, numVirtProcs);
|
||||
}
|
||||
|
||||
miscRegFile.clear();
|
||||
|
||||
lastRunningCycle = curTick;
|
||||
contextSwitch = false;
|
||||
|
||||
|
@ -461,7 +456,10 @@ InOrderCPU::readFunctional(Addr addr, uint32_t &buffer)
|
|||
void
|
||||
InOrderCPU::reset()
|
||||
{
|
||||
miscRegFile.reset(coreType, numThreads, numVirtProcs, dynamic_cast<BaseCPU*>(this));
|
||||
for (int i = 0; i < numThreads; i++) {
|
||||
isa[i].reset(coreType, numThreads,
|
||||
numVirtProcs, dynamic_cast<BaseCPU*>(this));
|
||||
}
|
||||
}
|
||||
|
||||
Port*
|
||||
|
@ -966,25 +964,25 @@ InOrderCPU::setRegOtherThread(unsigned reg_idx, const MiscReg &val,
|
|||
MiscReg
|
||||
InOrderCPU::readMiscRegNoEffect(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return miscRegFile.readRegNoEffect(misc_reg, tid);
|
||||
return isa[tid].readMiscRegNoEffect(misc_reg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
InOrderCPU::readMiscReg(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return miscRegFile.readReg(misc_reg, tcBase(tid), tid);
|
||||
return isa[tid].readMiscReg(misc_reg, tcBase(tid));
|
||||
}
|
||||
|
||||
void
|
||||
InOrderCPU::setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
|
||||
{
|
||||
miscRegFile.setRegNoEffect(misc_reg, val, tid);
|
||||
isa[tid].setMiscRegNoEffect(misc_reg, val);
|
||||
}
|
||||
|
||||
void
|
||||
InOrderCPU::setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
|
||||
{
|
||||
miscRegFile.setReg(misc_reg, val, tcBase(tid), tid);
|
||||
isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <vector>
|
||||
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/types.hh"
|
||||
#include "base/statistics.hh"
|
||||
#include "base/timebuf.hh"
|
||||
#include "base/types.hh"
|
||||
|
@ -76,8 +77,8 @@ class InOrderCPU : public BaseCPU
|
|||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegBits FloatRegBits;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
typedef TheISA::RegFile RegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
|
||||
//DynInstPtr TypeDefs
|
||||
typedef ThePipeline::DynInstPtr DynInstPtr;
|
||||
|
@ -259,7 +260,9 @@ class InOrderCPU : public BaseCPU
|
|||
/** The Register File for the CPU */
|
||||
TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];;
|
||||
TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];;
|
||||
TheISA::MiscRegFile miscRegFile;
|
||||
|
||||
/** ISA state */
|
||||
TheISA::ISA isa[ThePipeline::MaxThreads];
|
||||
|
||||
/** Dependency Tracker for Integer & Floating Point Regs */
|
||||
RegDepMap archRegDepMap[ThePipeline::MaxThreads];
|
||||
|
|
|
@ -211,6 +211,12 @@ class InOrderThreadContext : public ThreadContext
|
|||
* write might have as defined by the architecture. */
|
||||
virtual void setMiscReg(int misc_reg, const MiscReg &val);
|
||||
|
||||
virtual int flattenIntIndex(int reg)
|
||||
{ return cpu->isa[thread->readTid()].flattenIntIndex(reg); }
|
||||
|
||||
virtual int flattenFloatIndex(int reg)
|
||||
{ return cpu->isa[thread->readTid()].flattenFloatIndex(reg); }
|
||||
|
||||
virtual void activateContext(int delay)
|
||||
{ cpu->activateContext(thread->readTid(), delay); }
|
||||
|
||||
|
|
|
@ -1180,14 +1180,14 @@ template <class Impl>
|
|||
TheISA::MiscReg
|
||||
FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return this->regFile.readMiscRegNoEffect(misc_reg, tid);
|
||||
return this->isa[tid].readMiscRegNoEffect(misc_reg);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
TheISA::MiscReg
|
||||
FullO3CPU<Impl>::readMiscReg(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return this->regFile.readMiscReg(misc_reg, tid);
|
||||
return this->isa[tid].readMiscReg(misc_reg, tcBase(tid));
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -1195,7 +1195,7 @@ void
|
|||
FullO3CPU<Impl>::setMiscRegNoEffect(int misc_reg,
|
||||
const TheISA::MiscReg &val, ThreadID tid)
|
||||
{
|
||||
this->regFile.setMiscRegNoEffect(misc_reg, val, tid);
|
||||
this->isa[tid].setMiscRegNoEffect(misc_reg, val);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
@ -1203,7 +1203,7 @@ void
|
|||
FullO3CPU<Impl>::setMiscReg(int misc_reg,
|
||||
const TheISA::MiscReg &val, ThreadID tid)
|
||||
{
|
||||
this->regFile.setMiscReg(misc_reg, val, tid);
|
||||
this->isa[tid].setMiscReg(misc_reg, val, tcBase(tid));
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
|
|
|
@ -395,11 +395,11 @@ class FullO3CPU : public BaseO3CPU
|
|||
|
||||
/** Get instruction asid. */
|
||||
int getInstAsid(ThreadID tid)
|
||||
{ return regFile.miscRegs[tid].getInstAsid(); }
|
||||
{ return isa[tid].instAsid(); }
|
||||
|
||||
/** Get data asid. */
|
||||
int getDataAsid(ThreadID tid)
|
||||
{ return regFile.miscRegs[tid].getDataAsid(); }
|
||||
{ return isa[tid].dataAsid(); }
|
||||
#else
|
||||
/** Get instruction asid. */
|
||||
int getInstAsid(ThreadID tid)
|
||||
|
@ -603,6 +603,8 @@ class FullO3CPU : public BaseO3CPU
|
|||
/** Integer Register Scoreboard */
|
||||
Scoreboard scoreboard;
|
||||
|
||||
TheISA::ISA isa[Impl::MaxThreads];
|
||||
|
||||
public:
|
||||
/** Enum to give each stage a specific index, so when calling
|
||||
* activateStage() or deactivateStage(), they can specify which stage
|
||||
|
|
|
@ -57,8 +57,6 @@ class PhysRegFile
|
|||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegBits FloatRegBits;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
|
||||
typedef union {
|
||||
FloatReg d;
|
||||
|
@ -230,30 +228,6 @@ class PhysRegFile
|
|||
floatRegFile[reg_idx].q = val;
|
||||
}
|
||||
|
||||
MiscReg
|
||||
readMiscRegNoEffect(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return miscRegs[tid].readRegNoEffect(misc_reg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
readMiscReg(int misc_reg, ThreadID tid)
|
||||
{
|
||||
return miscRegs[tid].readReg(misc_reg, cpu->tcBase(tid));
|
||||
}
|
||||
|
||||
void
|
||||
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid)
|
||||
{
|
||||
miscRegs[tid].setRegNoEffect(misc_reg, val);
|
||||
}
|
||||
|
||||
void
|
||||
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid)
|
||||
{
|
||||
miscRegs[tid].setReg(misc_reg, val, cpu->tcBase(tid));
|
||||
}
|
||||
|
||||
public:
|
||||
/** (signed) integer register file. */
|
||||
IntReg *intRegFile;
|
||||
|
@ -261,9 +235,6 @@ class PhysRegFile
|
|||
/** Floating point register file. */
|
||||
PhysFloatReg *floatRegFile;
|
||||
|
||||
/** Miscellaneous register file. */
|
||||
MiscRegFile miscRegs[Impl::MaxThreads];
|
||||
|
||||
#if FULL_SYSTEM
|
||||
private:
|
||||
int intrflag; // interrupt flag
|
||||
|
@ -289,10 +260,6 @@ PhysRegFile<Impl>::PhysRegFile(O3CPU *_cpu, unsigned _numPhysicalIntRegs,
|
|||
intRegFile = new IntReg[numPhysicalIntRegs];
|
||||
floatRegFile = new PhysFloatReg[numPhysicalFloatRegs];
|
||||
|
||||
for (int i = 0; i < Impl::MaxThreads; ++i) {
|
||||
miscRegs[i].clear();
|
||||
}
|
||||
|
||||
memset(intRegFile, 0, sizeof(IntReg) * numPhysicalIntRegs);
|
||||
memset(floatRegFile, 0, sizeof(PhysFloatReg) * numPhysicalFloatRegs);
|
||||
}
|
||||
|
|
|
@ -959,11 +959,11 @@ DefaultRename<Impl>::renameSrcRegs(DynInstPtr &inst, ThreadID tid)
|
|||
RegIndex src_reg = inst->srcRegIdx(src_idx);
|
||||
RegIndex flat_src_reg = src_reg;
|
||||
if (src_reg < TheISA::FP_Base_DepTag) {
|
||||
flat_src_reg = TheISA::flattenIntIndex(inst->tcBase(), src_reg);
|
||||
flat_src_reg = inst->tcBase()->flattenIntIndex(src_reg);
|
||||
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)src_reg, (int)flat_src_reg);
|
||||
} else if (src_reg < TheISA::Ctrl_Base_DepTag) {
|
||||
src_reg = src_reg - TheISA::FP_Base_DepTag;
|
||||
flat_src_reg = TheISA::flattenFloatIndex(inst->tcBase(), src_reg);
|
||||
flat_src_reg = inst->tcBase()->flattenFloatIndex(src_reg);
|
||||
flat_src_reg += TheISA::NumIntRegs;
|
||||
} else {
|
||||
flat_src_reg = src_reg - TheISA::FP_Base_DepTag + TheISA::NumIntRegs;
|
||||
|
@ -1009,7 +1009,7 @@ DefaultRename<Impl>::renameDestRegs(DynInstPtr &inst, ThreadID tid)
|
|||
RegIndex flat_dest_reg = dest_reg;
|
||||
if (dest_reg < TheISA::FP_Base_DepTag) {
|
||||
// Integer registers are flattened.
|
||||
flat_dest_reg = TheISA::flattenIntIndex(inst->tcBase(), dest_reg);
|
||||
flat_dest_reg = inst->tcBase()->flattenIntIndex(dest_reg);
|
||||
DPRINTF(Rename, "Flattening index %d to %d.\n", (int)dest_reg, (int)flat_dest_reg);
|
||||
} else {
|
||||
// Floating point and Miscellaneous registers need their indexes
|
||||
|
|
|
@ -226,6 +226,9 @@ class O3ThreadContext : public ThreadContext
|
|||
* write might have as defined by the architecture. */
|
||||
virtual void setMiscReg(int misc_reg, const MiscReg &val);
|
||||
|
||||
virtual int flattenIntIndex(int reg);
|
||||
virtual int flattenFloatIndex(int reg);
|
||||
|
||||
/** Returns the number of consecutive store conditional failures. */
|
||||
// @todo: Figure out where these store cond failures should go.
|
||||
virtual unsigned readStCondFailures()
|
||||
|
|
|
@ -272,7 +272,7 @@ template <class Impl>
|
|||
uint64_t
|
||||
O3ThreadContext<Impl>::readIntReg(int reg_idx)
|
||||
{
|
||||
reg_idx = TheISA::flattenIntIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
|
||||
return cpu->readArchIntReg(reg_idx, thread->threadId());
|
||||
}
|
||||
|
||||
|
@ -280,7 +280,7 @@ template <class Impl>
|
|||
TheISA::FloatReg
|
||||
O3ThreadContext<Impl>::readFloatReg(int reg_idx, int width)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
switch(width) {
|
||||
case 32:
|
||||
return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
|
||||
|
@ -296,7 +296,7 @@ template <class Impl>
|
|||
TheISA::FloatReg
|
||||
O3ThreadContext<Impl>::readFloatReg(int reg_idx)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
return cpu->readArchFloatRegSingle(reg_idx, thread->threadId());
|
||||
}
|
||||
|
||||
|
@ -305,7 +305,7 @@ TheISA::FloatRegBits
|
|||
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx, int width)
|
||||
{
|
||||
DPRINTF(Fault, "Reading floatint register through the TC!\n");
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
|
||||
}
|
||||
|
||||
|
@ -313,7 +313,7 @@ template <class Impl>
|
|||
TheISA::FloatRegBits
|
||||
O3ThreadContext<Impl>::readFloatRegBits(int reg_idx)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
return cpu->readArchFloatRegInt(reg_idx, thread->threadId());
|
||||
}
|
||||
|
||||
|
@ -321,7 +321,7 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setIntReg(int reg_idx, uint64_t val)
|
||||
{
|
||||
reg_idx = TheISA::flattenIntIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenIntIndex(reg_idx);
|
||||
cpu->setArchIntReg(reg_idx, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
|
@ -334,7 +334,7 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val, int width)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
switch(width) {
|
||||
case 32:
|
||||
cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
|
||||
|
@ -354,7 +354,7 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setFloatReg(int reg_idx, FloatReg val)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
cpu->setArchFloatRegSingle(reg_idx, val, thread->threadId());
|
||||
|
||||
if (!thread->trapPending && !thread->inSyscall) {
|
||||
|
@ -368,7 +368,7 @@ O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val,
|
|||
int width)
|
||||
{
|
||||
DPRINTF(Fault, "Setting floatint register through the TC!\n");
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
|
@ -381,7 +381,7 @@ template <class Impl>
|
|||
void
|
||||
O3ThreadContext<Impl>::setFloatRegBits(int reg_idx, FloatRegBits val)
|
||||
{
|
||||
reg_idx = TheISA::flattenFloatIndex(this, reg_idx);
|
||||
reg_idx = cpu->isa[thread->threadId()].flattenFloatIndex(reg_idx);
|
||||
cpu->setArchFloatRegInt(reg_idx, val, thread->threadId());
|
||||
|
||||
// Squash if we're not already in a state update mode.
|
||||
|
@ -438,6 +438,20 @@ O3ThreadContext<Impl>::setNextMicroPC(uint64_t val)
|
|||
}
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
int
|
||||
O3ThreadContext<Impl>::flattenIntIndex(int reg)
|
||||
{
|
||||
return cpu->isa[thread->threadId()].flattenIntIndex(reg);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
int
|
||||
O3ThreadContext<Impl>::flattenFloatIndex(int reg)
|
||||
{
|
||||
return cpu->isa[thread->threadId()].flattenFloatIndex(reg);
|
||||
}
|
||||
|
||||
template <class Impl>
|
||||
void
|
||||
O3ThreadContext<Impl>::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
|
||||
|
|
|
@ -32,6 +32,7 @@
|
|||
#ifndef __CPU_SIMPLE_THREAD_HH__
|
||||
#define __CPU_SIMPLE_THREAD_HH__
|
||||
|
||||
#include "arch/isa.hh"
|
||||
#include "arch/isa_traits.hh"
|
||||
#include "arch/regfile.hh"
|
||||
#include "arch/tlb.hh"
|
||||
|
@ -90,7 +91,6 @@ class SimpleThread : public ThreadState
|
|||
protected:
|
||||
typedef TheISA::RegFile RegFile;
|
||||
typedef TheISA::MachInst MachInst;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegBits FloatRegBits;
|
||||
|
@ -99,6 +99,7 @@ class SimpleThread : public ThreadState
|
|||
|
||||
protected:
|
||||
RegFile regs; // correct-path register context
|
||||
TheISA::ISA isa; // one "instance" of the current ISA.
|
||||
|
||||
public:
|
||||
// pointer to CPU associated with this SimpleThread
|
||||
|
@ -164,8 +165,8 @@ class SimpleThread : public ThreadState
|
|||
}
|
||||
|
||||
#if FULL_SYSTEM
|
||||
int getInstAsid() { return regs.instAsid(); }
|
||||
int getDataAsid() { return regs.dataAsid(); }
|
||||
int getInstAsid() { return isa.instAsid(); }
|
||||
int getDataAsid() { return isa.dataAsid(); }
|
||||
|
||||
void dumpFuncProfile();
|
||||
|
||||
|
@ -229,61 +230,61 @@ class SimpleThread : public ThreadState
|
|||
//
|
||||
uint64_t readIntReg(int reg_idx)
|
||||
{
|
||||
int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenIntIndex(reg_idx);
|
||||
return regs.readIntReg(flatIndex);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(int reg_idx, int width)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
return regs.readFloatReg(flatIndex, width);
|
||||
}
|
||||
|
||||
FloatReg readFloatReg(int reg_idx)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
return regs.readFloatReg(flatIndex);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(int reg_idx, int width)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
return regs.readFloatRegBits(flatIndex, width);
|
||||
}
|
||||
|
||||
FloatRegBits readFloatRegBits(int reg_idx)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
return regs.readFloatRegBits(flatIndex);
|
||||
}
|
||||
|
||||
void setIntReg(int reg_idx, uint64_t val)
|
||||
{
|
||||
int flatIndex = TheISA::flattenIntIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenIntIndex(reg_idx);
|
||||
regs.setIntReg(flatIndex, val);
|
||||
}
|
||||
|
||||
void setFloatReg(int reg_idx, FloatReg val, int width)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
regs.setFloatReg(flatIndex, val, width);
|
||||
}
|
||||
|
||||
void setFloatReg(int reg_idx, FloatReg val)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
regs.setFloatReg(flatIndex, val);
|
||||
}
|
||||
|
||||
void setFloatRegBits(int reg_idx, FloatRegBits val, int width)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
regs.setFloatRegBits(flatIndex, val, width);
|
||||
}
|
||||
|
||||
void setFloatRegBits(int reg_idx, FloatRegBits val)
|
||||
{
|
||||
int flatIndex = TheISA::flattenFloatIndex(getTC(), reg_idx);
|
||||
int flatIndex = isa.flattenFloatIndex(reg_idx);
|
||||
regs.setFloatRegBits(flatIndex, val);
|
||||
}
|
||||
|
||||
|
@ -340,25 +341,37 @@ class SimpleThread : public ThreadState
|
|||
MiscReg
|
||||
readMiscRegNoEffect(int misc_reg, ThreadID tid = 0)
|
||||
{
|
||||
return regs.readMiscRegNoEffect(misc_reg);
|
||||
return isa.readMiscRegNoEffect(misc_reg);
|
||||
}
|
||||
|
||||
MiscReg
|
||||
readMiscReg(int misc_reg, ThreadID tid = 0)
|
||||
{
|
||||
return regs.readMiscReg(misc_reg, tc);
|
||||
return isa.readMiscReg(misc_reg, tc);
|
||||
}
|
||||
|
||||
void
|
||||
setMiscRegNoEffect(int misc_reg, const MiscReg &val, ThreadID tid = 0)
|
||||
{
|
||||
return regs.setMiscRegNoEffect(misc_reg, val);
|
||||
return isa.setMiscRegNoEffect(misc_reg, val);
|
||||
}
|
||||
|
||||
void
|
||||
setMiscReg(int misc_reg, const MiscReg &val, ThreadID tid = 0)
|
||||
{
|
||||
return regs.setMiscReg(misc_reg, val, tc);
|
||||
return isa.setMiscReg(misc_reg, val, tc);
|
||||
}
|
||||
|
||||
int
|
||||
flattenIntIndex(int reg)
|
||||
{
|
||||
return isa.flattenIntIndex(reg);
|
||||
}
|
||||
|
||||
int
|
||||
flattenFloatIndex(int reg)
|
||||
{
|
||||
return isa.flattenFloatIndex(reg);
|
||||
}
|
||||
|
||||
unsigned readStCondFailures() { return storeCondFailures; }
|
||||
|
|
|
@ -84,7 +84,6 @@ class ThreadContext
|
|||
typedef TheISA::IntReg IntReg;
|
||||
typedef TheISA::FloatReg FloatReg;
|
||||
typedef TheISA::FloatRegBits FloatRegBits;
|
||||
typedef TheISA::MiscRegFile MiscRegFile;
|
||||
typedef TheISA::MiscReg MiscReg;
|
||||
public:
|
||||
|
||||
|
@ -234,6 +233,9 @@ class ThreadContext
|
|||
|
||||
virtual void setMiscReg(int misc_reg, const MiscReg &val) = 0;
|
||||
|
||||
virtual int flattenIntIndex(int reg) = 0;
|
||||
virtual int flattenFloatIndex(int reg) = 0;
|
||||
|
||||
virtual uint64_t
|
||||
readRegOtherThread(int misc_reg, ThreadID tid)
|
||||
{
|
||||
|
@ -434,6 +436,12 @@ class ProxyThreadContext : public ThreadContext
|
|||
void setMiscReg(int misc_reg, const MiscReg &val)
|
||||
{ return actualTC->setMiscReg(misc_reg, val); }
|
||||
|
||||
int flattenIntIndex(int reg)
|
||||
{ return actualTC->flattenIntIndex(reg); }
|
||||
|
||||
int flattenFloatIndex(int reg)
|
||||
{ return actualTC->flattenFloatIndex(reg); }
|
||||
|
||||
unsigned readStCondFailures()
|
||||
{ return actualTC->readStCondFailures(); }
|
||||
|
||||
|
|
|
@ -55,6 +55,7 @@ class Tru64 {};
|
|||
#include <string.h> // for memset()
|
||||
#include <unistd.h>
|
||||
|
||||
#include "arch/alpha/miscregfile.hh"
|
||||
#include "cpu/base.hh"
|
||||
#include "sim/core.hh"
|
||||
#include "sim/syscall_emul.hh"
|
||||
|
|
Loading…
Reference in a new issue