alpha: Small removal of dead comments/code from alpha ISA

Committed by: Nilay Vaish <nilay@cs.wisc.edu>
This commit is contained in:
Paul Rosenfeld 2014-03-12 07:03:22 -05:00
parent 62fe81e9c1
commit 32bf74cb8e
2 changed files with 0 additions and 20 deletions

View file

@ -465,27 +465,14 @@ def LoadStoreBase(name, Name, ea_code, memacc_code, mem_flags, inst_flags,
mem_flags = makeList(mem_flags) mem_flags = makeList(mem_flags)
inst_flags = makeList(inst_flags) inst_flags = makeList(inst_flags)
# Some CPU models execute the memory operation as an atomic unit,
# while others want to separate them into an effective address
# computation and a memory access operation. As a result, we need
# to generate three StaticInst objects. Note that the latter two
# are nested inside the larger "atomic" one.
# Generate InstObjParams for each of the three objects. Note that
# they differ only in the set of code objects contained (which in
# turn affects the object's overall operand list).
iop = InstObjParams(name, Name, base_class, iop = InstObjParams(name, Name, base_class,
{ 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code }, { 'ea_code':ea_code, 'memacc_code':memacc_code, 'postacc_code':postacc_code },
inst_flags) inst_flags)
memacc_iop = InstObjParams(name, Name, base_class,
{ 'memacc_code':memacc_code, 'postacc_code':postacc_code },
inst_flags)
if mem_flags: if mem_flags:
mem_flags = [ 'Request::%s' % flag for flag in mem_flags ] mem_flags = [ 'Request::%s' % flag for flag in mem_flags ]
s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';' s = '\n\tmemAccessFlags = ' + string.join(mem_flags, '|') + ';'
iop.constructor += s iop.constructor += s
memacc_iop.constructor += s
# select templates # select templates

View file

@ -54,13 +54,6 @@
class Packet; class Packet;
/**
* Mostly implementation & ISA specific AlphaDynInst. As with most
* other classes in the new CPU model, it is templated on the Impl to
* allow for passing in of all types, such as the CPU type and the ISA
* type. The AlphaDynInst serves as the primary interface to the CPU
* for instructions that are executing.
*/
template <class Impl> template <class Impl>
class BaseO3DynInst : public BaseDynInst<Impl> class BaseO3DynInst : public BaseDynInst<Impl>
{ {