Now timing reads work in single level of cache with simple cpu
src/mem/cache/base_cache.cc: src/mem/cache/base_cache.hh: src/mem/cache/cache.hh: Changes to handle timing reads in Simple CPU (blocking buffers) --HG-- extra : convert_revision : a2e7d4287d7cdfd1bbf9c929ecbeafde499a5b9f
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4201ec84b2
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31
src/mem/cache/base_cache.cc
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31
src/mem/cache/base_cache.cc
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@ -98,6 +98,37 @@ BaseCache::CachePort::clearBlocked()
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blocked = false;
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blocked = false;
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}
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}
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BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
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: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
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{
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this->setFlags(AutoDelete);
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pkt = NULL;
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}
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BaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
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: Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
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{
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this->setFlags(AutoDelete);
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}
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void
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BaseCache::CacheEvent::process()
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{
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if (!pkt)
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{
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if (!cachePort->isCpuSide)
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pkt = cachePort->cache->getPacket();
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//Else get coherence req
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}
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cachePort->sendTiming(pkt);
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}
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const char *
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BaseCache::CacheEvent::description()
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{
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return "timing event\n";
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}
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Port*
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Port*
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BaseCache::getPort(const std::string &if_name, int idx)
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BaseCache::getPort(const std::string &if_name, int idx)
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{
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{
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32
src/mem/cache/base_cache.hh
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32
src/mem/cache/base_cache.hh
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@ -79,9 +79,9 @@ class BaseCache : public MemObject
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{
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{
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class CachePort : public Port
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class CachePort : public Port
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{
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{
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public:
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BaseCache *cache;
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BaseCache *cache;
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public:
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CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
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CachePort(const std::string &_name, BaseCache *_cache, bool _isCpuSide);
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protected:
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protected:
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@ -110,10 +110,11 @@ class BaseCache : public MemObject
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struct CacheEvent : public Event
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struct CacheEvent : public Event
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{
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{
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Packet *pkt;
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CachePort *cachePort;
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CachePort *cachePort;
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Packet *pkt;
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CacheEvent(Packet *pkt, CachePort *cachePort);
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CacheEvent(CachePort *_cachePort);
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CacheEvent(CachePort *_cachePort, Packet *_pkt);
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void process();
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void process();
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const char *description();
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const char *description();
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};
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};
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@ -147,6 +148,11 @@ class BaseCache : public MemObject
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fatal("No implementation");
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fatal("No implementation");
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}
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}
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virtual Packet *getPacket()
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{
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fatal("No implementation");
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}
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/**
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/**
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* Bit vector of the blocking reasons for the access path.
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* Bit vector of the blocking reasons for the access path.
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* @sa #BlockedCause
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* @sa #BlockedCause
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@ -388,7 +394,6 @@ class BaseCache : public MemObject
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if (!isBlockedForSnoop()) {
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if (!isBlockedForSnoop()) {
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memSidePort->clearBlocked();
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memSidePort->clearBlocked();
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}
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}
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}
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}
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/**
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/**
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@ -407,10 +412,13 @@ class BaseCache : public MemObject
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*/
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*/
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void setMasterRequest(RequestCause cause, Tick time)
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void setMasterRequest(RequestCause cause, Tick time)
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{
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{
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if (!doMasterRequest())
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{
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BaseCache::CacheEvent * reqCpu = new BaseCache::CacheEvent(memSidePort);
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reqCpu->schedule(time);
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}
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uint8_t flag = 1<<cause;
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uint8_t flag = 1<<cause;
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masterRequests |= flag;
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masterRequests |= flag;
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assert("Implement\n" && 0);
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// mi->pktuest(time);
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}
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}
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/**
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/**
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@ -462,8 +470,10 @@ class BaseCache : public MemObject
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*/
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*/
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void respond(Packet *pkt, Tick time)
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void respond(Packet *pkt, Tick time)
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{
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{
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assert("Implement\n" && 0);
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pkt->makeTimingResponse();
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// si->respond(pkt,time);
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pkt->result = Packet::Success;
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CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
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reqCpu->schedule(time);
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}
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}
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/**
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/**
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@ -476,8 +486,10 @@ class BaseCache : public MemObject
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if (!pkt->req->isUncacheable()) {
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if (!pkt->req->isUncacheable()) {
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missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
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missLatency[pkt->cmdToIndex()][pkt->req->getThreadNum()] += time - pkt->time;
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}
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}
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assert("Implement\n" && 0);
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pkt->makeTimingResponse();
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// si->respond(pkt,time);
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pkt->result = Packet::Success;
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CacheEvent *reqCpu = new CacheEvent(cpuSidePort, pkt);
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reqCpu->schedule(time);
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}
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}
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/**
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/**
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13
src/mem/cache/cache.hh
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13
src/mem/cache/cache.hh
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@ -168,7 +168,7 @@ class Cache : public BaseCache
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* Selects a request to send on the bus.
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* Selects a request to send on the bus.
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* @return The memory request to service.
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* @return The memory request to service.
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*/
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*/
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Packet * getPacket();
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virtual Packet * getPacket();
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/**
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/**
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* Was the request was sent successfully?
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* Was the request was sent successfully?
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@ -241,17 +241,6 @@ class Cache : public BaseCache
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return missQueue->getMisses();
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return missQueue->getMisses();
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}
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}
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/**
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* Send a response to the slave interface.
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* @param req The request being responded to.
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* @param time The time the response is ready.
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*/
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void respond(Packet * &pkt, Tick time)
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{
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//si->respond(pkt,time);
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cpuSidePort->sendAtomic(pkt);
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}
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/**
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/**
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* Perform the access specified in the request and return the estimated
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* Perform the access specified in the request and return the estimated
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* time of completion. This function can either update the hierarchy state
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* time of completion. This function can either update the hierarchy state
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