Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem --HG-- extra : convert_revision : fa1e361fcae10fe7a91118007faeeabe3fecba2a
This commit is contained in:
Ali Saidi
commit
329db76e47
6 changed files with 202 additions and 0 deletions
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@ -0,0 +1,68 @@
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[root]
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type=Root
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children=system
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checkpoint=
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clock=1000000000000
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max_tick=0
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output_file=cout
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progress_interval=0
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[system]
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type=System
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children=cpu membus physmem
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mem_mode=atomic
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physmem=system.physmem
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[system.cpu]
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type=AtomicSimpleCPU
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children=workload
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clock=1
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cpu_id=0
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defer_registration=false
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function_trace=false
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function_trace_start=0
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max_insts_all_threads=0
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max_insts_any_thread=0
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max_loads_all_threads=0
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max_loads_any_thread=0
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phase=0
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progress_interval=0
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simulate_stalls=false
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system=system
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width=1
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workload=system.cpu.workload
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dcache_port=system.membus.port[2]
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icache_port=system.membus.port[1]
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[system.cpu.workload]
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type=LiveProcess
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cmd=insttest
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cwd=
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egid=100
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env=
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euid=100
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executable=tests/test-progs/insttest/bin/sparc/linux/insttest
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gid=100
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input=cin
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output=cout
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pid=100
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ppid=99
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system=system
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uid=100
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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responder_set=false
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width=64
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port=system.physmem.port system.cpu.icache_port system.cpu.dcache_port
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[system.physmem]
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type=PhysicalMemory
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file=
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latency=1
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range=0:134217727
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zero=false
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port=system.membus.port[0]
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@ -0,0 +1,60 @@
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[root]
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type=Root
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clock=1000000000000
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max_tick=0
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progress_interval=0
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output_file=cout
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[system.physmem]
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type=PhysicalMemory
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file=
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range=[0,134217727]
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latency=1
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zero=false
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[system]
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type=System
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physmem=system.physmem
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mem_mode=atomic
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[system.membus]
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type=Bus
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bus_id=0
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clock=1000
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width=64
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responder_set=false
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[system.cpu.workload]
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type=LiveProcess
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cmd=insttest
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executable=tests/test-progs/insttest/bin/sparc/linux/insttest
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input=cin
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output=cout
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env=
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cwd=
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system=system
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uid=100
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euid=100
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gid=100
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egid=100
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pid=100
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ppid=99
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[system.cpu]
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type=AtomicSimpleCPU
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max_insts_any_thread=0
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max_insts_all_threads=0
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max_loads_any_thread=0
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max_loads_all_threads=0
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progress_interval=0
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system=system
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cpu_id=0
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workload=system.cpu.workload
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clock=1
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phase=0
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defer_registration=false
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width=1
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function_trace=false
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function_trace_start=0
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simulate_stalls=false
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@ -0,0 +1,18 @@
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---------- Begin Simulation Statistics ----------
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host_inst_rate 104057 # Simulator instruction rate (inst/s)
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host_mem_usage 179368 # Number of bytes of host memory used
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host_seconds 0.10 # Real time elapsed on the host
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host_tick_rate 103746 # Simulator tick rate (ticks/s)
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sim_freq 1000000000000 # Frequency of simulated ticks
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sim_insts 10367 # Number of instructions simulated
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sim_seconds 0.000000 # Number of seconds simulated
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sim_ticks 10366 # Number of ticks simulated
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system.cpu.idle_fraction 0 # Percentage of idle cycles
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system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles
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system.cpu.numCycles 10367 # number of cpu cycles simulated
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system.cpu.num_insts 10367 # Number of instructions executed
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system.cpu.num_refs 2607 # Number of memory references
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system.cpu.workload.PROG:num_syscalls 8 # Number of system calls
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---------- End Simulation Statistics ----------
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@ -0,0 +1,4 @@
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warn: More than two loadable segments in ELF object.
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warn: Ignoring segment @ 0x0 length 0x0.
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0: system.remote_gdb.listener: listening for remote gdb #0 on port 7000
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warn: Entering event queue @ 0. Starting simulation...
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22
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
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22
tests/quick/02.insttest/ref/sparc/linux/simple-atomic/stdout
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Begining test of difficult SPARC instructions...
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LDSTUB: Passed
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SWAP: Passed
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CAS FAIL: Passed
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CAS WORK: Passed
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CASX FAIL: Passed
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CASX WORK: Passed
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LDTX: Passed
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LDTW: Passed
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Done
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M5 Simulator System
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Copyright (c) 2001-2006
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The Regents of The University of Michigan
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All Rights Reserved
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M5 compiled Mar 6 2007 15:43:35
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M5 started Tue Mar 6 15:52:39 2007
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M5 executing on zeep
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command line: build/SPARC_SE/m5.debug -d build/SPARC_SE/tests/debug/quick/02.insttest/sparc/linux/simple-atomic tests/run.py quick/02.insttest/sparc/linux/simple-atomic
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Exiting @ tick 10366 because target called exit()
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30
tests/quick/02.insttest/test.py
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30
tests/quick/02.insttest/test.py
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# Copyright (c) 2007 The Regents of The University of Michigan
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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# Authors: Ali Saidi
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root.system.cpu.workload = LiveProcess(cmd = 'insttest',
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executable = binpath('insttest'))
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