Fixes to get ALPHA_FS and ALPHA_SE to compile again.
--HG-- extra : convert_revision : 6e0913903d4cbda6f31bec3b5d725b9c08dc1419
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5 changed files with 22 additions and 11 deletions
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@ -121,14 +121,18 @@
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#include <string>
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#include <unistd.h>
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#include "config/full_system.hh"
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#if FULL_SYSTEM
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#include "arch/alpha/vtophys.hh"
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#endif
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#include "arch/alpha/kgdb.h"
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#include "arch/alpha/utility.hh"
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#include "arch/alpha/remote_gdb.hh"
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#include "arch/vtophys.hh"
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#include "base/intmath.hh"
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#include "base/remote_gdb.hh"
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#include "base/socket.hh"
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#include "base/trace.hh"
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#include "config/full_system.hh"
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#include "cpu/thread_context.hh"
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#include "cpu/static_inst.hh"
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#include "mem/physical.hh"
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@ -152,6 +156,9 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *c)
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bool
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RemoteGDB::acc(Addr va, size_t len)
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{
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#if !FULL_SYSTEM
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panic("acc function needs to be rewritten for SE mode\n");
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#else
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Addr last_va;
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va = TheISA::TruncPage(va);
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@ -191,6 +198,7 @@ RemoteGDB::acc(Addr va, size_t len)
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DPRINTF(GDBAcc, "acc: %#x mapping is valid\n", va);
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return true;
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#endif
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}
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///////////////////////////////////////////////////////////
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@ -121,9 +121,9 @@ namespace AlphaISA
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template <class TC>
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void zeroRegisters(TC *tc);
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#if FULL_SYSTEM
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// Alpha IPR register accessors
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inline bool PcPAL(Addr addr) { return addr & 0x1; }
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inline bool PcPAL(Addr addr) { return addr & 0x3; }
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#if FULL_SYSTEM
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////////////////////////////////////////////////////////////////////////
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//
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@ -73,8 +73,9 @@ class AlphaDynInst : public BaseDynInst<Impl>
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public:
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/** BaseDynInst constructor given a binary instruction. */
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AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num,
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O3CPU *cpu);
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AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
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Addr Pred_PC, Addr Pred_NPC,
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InstSeqNum seq_num, O3CPU *cpu);
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/** BaseDynInst constructor given a static inst pointer. */
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AlphaDynInst(StaticInstPtr &_staticInst);
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@ -31,9 +31,10 @@
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#include "cpu/o3/alpha/dyn_inst.hh"
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template <class Impl>
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AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC,
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AlphaDynInst<Impl>::AlphaDynInst(ExtMachInst inst, Addr PC, Addr NPC,
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Addr Pred_PC, Addr Pred_NPC,
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InstSeqNum seq_num, O3CPU *cpu)
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: BaseDynInst<Impl>(inst, PC, Pred_PC, seq_num, cpu)
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: BaseDynInst<Impl>(inst, PC, NPC, Pred_PC, Pred_NPC, seq_num, cpu)
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{
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initVars();
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}
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@ -1256,10 +1256,11 @@ DefaultFetch<Impl>::fetch(bool &status_change)
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ext_inst = TheISA::NoopMachInst;
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// Create a new DynInst from the dummy nop.
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DynInstPtr instruction = new DynInst(ext_inst, fetch_PC,
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next_PC,
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DynInstPtr instruction = new DynInst(ext_inst,
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fetch_PC, fetch_NPC,
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next_PC, next_NPC,
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inst_seq, cpu);
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instruction->setPredTarg(next_PC + instSize);
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instruction->setPredTarg(next_PC, next_NPC);
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instruction->setTid(tid);
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instruction->setASID(tid);
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