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ARM: Squash state on FPSCR stride or len write.

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This commit is contained in:
Ali Saidi 2011-02-23 15:10:49 -06:00
parent bb319a589e
commit 326191adc9
1 changed files with 2 additions and 1 deletions
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3
src/arch/arm/isa/insts/fp.isa
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@ -209,7 +209,8 @@ let {{
{ "code": vmsrFpscrCode, { "code": vmsrFpscrCode,
"predicate_test": predicateTest, "predicate_test": predicateTest,
"op_class": "SimdFloatMiscOp" }, "op_class": "SimdFloatMiscOp" },
["IsSerializeAfter","IsNonSpeculative"]) ["IsSerializeAfter","IsNonSpeculative",
"IsSquashAfter"])
header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop); header_output += FpRegRegOpDeclare.subst(vmsrFpscrIop);
decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop); decoder_output += FpRegRegOpConstructor.subst(vmsrFpscrIop);
exec_output += PredOpExecute.subst(vmsrFpscrIop); exec_output += PredOpExecute.subst(vmsrFpscrIop);